Datasheet 8V97003 (IDT) - 6

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List of Tables
Table 1. Pin Descriptions .. 8 Table 2. Pin Characteristics .. 10 Table 3. Supply Pins and Associated Current Return Paths... 10 Table 4. Absolute Maximum Ratings .. 11 Table 5. Recommended Operating Conditions... 11 Table 6. Thermal Characteristics .. 12 Table 7. Thermal Resistance θJA for 48-VFQFPN, Forced Convection... 12 Table 8. Power Supply DC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Case or Junction Temp.) ... 12 Table 9. Typical Current by Power Domain .. 13 Table 10. LVCMOS DC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Case or Junction Temp.) .. 14 Table 11. AC Characteristics, VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Maximum Case or Junction Temp.)... 15 Table 12. RF_OUT[A:B] Phase Noise Char., VDDx = 3.3V ±5%, TA = -40°C to +95°C (Not Exceeding Max. Case or Junction Temp.) ... 16 Table 13. Fractional Spurs Due to the Quantization Noise... 24 Table 14. Timing Requirements.. 28 Table 15. SPI Read / Write Cycle Timing Parameters.. 33 Table 16. Preface Registers ... 34 Table 17. Control Registers .. 34 Table 18. Status Registers.. 36 Table 19. Register Block Descriptions .. 37 Table 20. Preface Register Block ... 38 Table 21. Preface Register Bits .. 38 Table 22. Preface Register Description .. 39 Table 23. Feedback Divider Control Block.. 40 Table 24. Feedback Divider Control Register Bits .. 40 Table 25. Feedback Divider Control Register Description .. 41 Table 26. Phase Adjustments Control Register Block .. 42 Table 27. Phase Adjustments Control Register Bits ... 42 Table 28. Phase Adjustments Control Register Descriptions ... 42 Table 29. DSM Control Register Block ... 43 Table 30. DSM Control Register Bits .. 43 Table 31. DSM Control Register Descriptions .. 43 Table 32. Calibration Control Register Block .. 44 Table 33. Calibration Control Register Bits... 44 Table 34. Calibration Control Register Descriptions ... 44 Table 35. Band Select Clock Divider Control Register Block.. 46 Table 36. Band Select Clock Divider Control Register Bits... 46 Table 37. Band Select Clock Divider Control Register Descriptions... 46 Table 38. Lock Detect Control Register Block .. 47 Table 39. Lock Detect Control Register Bits ... 47 Table 40. Lock Detect Control Register Descriptions ... 47 Table 41. Power Down Control Register Block... 48 Table 42. Power Down Control Register Bits.. 48 Table 43. Power Down Control Register Descriptions.. 48 Table 44. Input Control Register Block ... 49 Table 45. Input Control Register Bits .. 49 Table 46. Input Control Register Descriptions .. 49 Table 47. Charge Pump Control Register Block ... 51 Table 48. Charge Pump Control Register Bits.. 51 ©2020 Renesas Electronics Corporation 6 January 20, 2020 Document Outline Description Typical Applications Features Simplified Block Diagram Block Diagram Contents List of Figures List of Tables Pin Assignments Pin Descriptions Absolute Maximum Ratings Recommended Operating Conditions Thermal Characteristics and Reliability Information DC Electrical Characteristics AC Electrical Characteristics Typical Performance Characteristics Theory of Operation Synthesizer Programming Reference Input Stage Input Reference Divider (R) Reference Doubler Reference Multiplier (MULT) Feedback Divider Phase and Frequency Detector (PFD) and Charge Pump PFD Frequency External Loop Filter Charge Pump High-Impedance Integrated Low Noise VCO Output Clock Distribution and Optional Output Doubler Output Matching Band Selection Disable Phase Adjust RF Output Power Output Phase Synchronization Power-Down Mode Default Power-Up Conditions VCO Calibration 3- or 4-Wire SPI Interface Description 3/4-Wire Mode Active Clock Edge Reset Least Significant Bit Position Addressing Read Operation Mirrored Register Bits Double-Buffered Registers Operation Protocols Register Map Register Block Descriptions Preface Registers Feedback Divider Control Registers Phase Adjustments Control Registers DSM Control Registers Calibration Control Registers Band Select Clock Divider Control Registers Lock Detect Control Registers Power Down Control Registers Input Control Registers Charge Pump Control Registers Re-Sync Control Registers Output Control Registers Status Registers Applications Information Loop Filter Calculations Recommendations for Unused Input and Output Pins Schematic Example Power Considerations Package Outline Drawings Marking Diagram Ordering Information Revision History