Datasheet S-34TS04L (ABLIC) - 6
| Manufacturer | ABLIC |
| Description | 2-wire Serial E2PROM With Temperature Sensor |
| Pages / Page | 38 / 6 — 2-WIRE SERIAL E2PROM WITH TEMPERATURE SENSOR S-34TS04L. AC Electrical … |
| File Format / Size | PDF / 523 Kb |
| Document Language | English |
2-WIRE SERIAL E2PROM WITH TEMPERATURE SENSOR S-34TS04L. AC Electrical Characteristics. Table 7 Measurement Conditions
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2-WIRE SERIAL E2PROM WITH TEMPERATURE SENSOR S-34TS04L
Rev.1.0_00_U
AC Electrical Characteristics Table 7 Measurement Conditions
Input pulse voltage Output reference voltage Input pulse voltage 0.2 × VDD to 0.8 × VDD 0.8 × VDD Input pulse rising / falling time 20 ns or less 0.7 × VDD Output reference voltage 0.3 × VDD to 0.7 × VDD Output load 100 pF 0.3 × VDD 0.2 × VDD
Figure 1 Input / Output Waveform during AC Measurement Table 8
Ta = −20°C to +125°C VDD = 1.7 V to 3.6 V VDD = 2.2 V to 3.6 V Item Symbol Unit fSCL = 100 kHz fSCL = 400 kHz fSCL = 1000 kHz Min. Max. Min. Max. Min. Max. SCL clock frequency fSCL 10 100 10 400 10 1000 kHz SCL clock time "L" tLOW 4.7 − 1.3 − 0.5 − μs SCL clock time "H" tHIGH 4.0 − 0.6 − 0.26 − μs SCL clock "L" timeout tTIMEOUT 25 35 25 35 25 35 ms SCL, SDA rising time tR 0.02 1.0 0.02 0.3 − 0.12 μs SCL, SDA falling time tF 0.02 0.3 0.02 0.3 − 0.12 μs Data input setup time tSU.DAT 250 − 100 − 50 − ns Data input hold time tHD.DI 0 − 0 − 0 − ns Data output hold time tHD.DAT 200 900 200 900 0 350 ns Start condition setup time tSU.STA 4.7 − 0.6 − 0.26 − μs Start condition hold time tHD.STA 4.0 − 0.6 − 0.26 − μs Stop condition setup time tSU.STO 4.0 − 0.6 − 0.26 − μs Bus release time tBUF 4.7 − 1.3 − 0.5 − μs Noise suppression time tI − 50 − 50 − 50 ns Power-off time tPOFF 1 − 1 − 1 − ms Initialize time tINIT 0.2 − 0.2 − 0.2 − ms t t HIGH t LOW F tR SCL tHD.STA t t t HD.DI SU.DAT SU.STA tSU.STO SDA (Input) tHD.DAT tBUF SDA (Output)
Figure 2 Bus Timing
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Rev.1.0_00_U
AC Electrical Characteristics Table 7 Measurement Conditions
Input pulse voltage Output reference voltage Input pulse voltage 0.2 × VDD to 0.8 × VDD 0.8 × VDD Input pulse rising / falling time 20 ns or less 0.7 × VDD Output reference voltage 0.3 × VDD to 0.7 × VDD Output load 100 pF 0.3 × VDD 0.2 × VDD
Figure 1 Input / Output Waveform during AC Measurement Table 8
Ta = −20°C to +125°C VDD = 1.7 V to 3.6 V VDD = 2.2 V to 3.6 V Item Symbol Unit fSCL = 100 kHz fSCL = 400 kHz fSCL = 1000 kHz Min. Max. Min. Max. Min. Max. SCL clock frequency fSCL 10 100 10 400 10 1000 kHz SCL clock time "L" tLOW 4.7 − 1.3 − 0.5 − μs SCL clock time "H" tHIGH 4.0 − 0.6 − 0.26 − μs SCL clock "L" timeout tTIMEOUT 25 35 25 35 25 35 ms SCL, SDA rising time tR 0.02 1.0 0.02 0.3 − 0.12 μs SCL, SDA falling time tF 0.02 0.3 0.02 0.3 − 0.12 μs Data input setup time tSU.DAT 250 − 100 − 50 − ns Data input hold time tHD.DI 0 − 0 − 0 − ns Data output hold time tHD.DAT 200 900 200 900 0 350 ns Start condition setup time tSU.STA 4.7 − 0.6 − 0.26 − μs Start condition hold time tHD.STA 4.0 − 0.6 − 0.26 − μs Stop condition setup time tSU.STO 4.0 − 0.6 − 0.26 − μs Bus release time tBUF 4.7 − 1.3 − 0.5 − μs Noise suppression time tI − 50 − 50 − 50 ns Power-off time tPOFF 1 − 1 − 1 − ms Initialize time tINIT 0.2 − 0.2 − 0.2 − ms t t HIGH t LOW F tR SCL tHD.STA t t t HD.DI SU.DAT SU.STA tSU.STO SDA (Input) tHD.DAT tBUF SDA (Output)
Figure 2 Bus Timing
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