Datasheet KSZ8895MLUB (Microchip)
| Manufacturer | Microchip |
| Description | Integrated 5-Port 10/100 Managed Switch |
| Pages / Page | 100 / 1 — KSZ8895MLUB. Integrated 5-Port 10/100 Managed Switch. Features. QoS/CoS … |
| File Format / Size | PDF / 1.5 Mb |
| Document Language | English |
KSZ8895MLUB. Integrated 5-Port 10/100 Managed Switch. Features. QoS/CoS Packet Prioritization Support. Advanced Switch Features
Model Line for this Datasheet
- KSZ8895FQXC KSZ8895FQXC-TR KSZ8895FQXCA KSZ8895FQXI KSZ8895FQXI-TR KSZ8895FQXIA KSZ8895ML KSZ8895MLUB KSZ8895MLUB-TR KSZ8895MLXC KSZ8895MLXC-TR KSZ8895MLXI KSZ8895MLXI-TR KSZ8895MQ KSZ8895MQI KSZ8895MQXC KSZ8895MQXC-TR KSZ8895MQXCA KSZ8895MQXI KSZ8895MQXI-TR KSZ8895MQXIA KSZ8895RQI KSZ8895RQXC KSZ8895RQXC-TR KSZ8895RQXCA KSZ8895RQXCA-TR KSZ8895RQXI KSZ8895RQXI-TR KSZ8895RQXIA SPNY801156 SPNY801159 SPNY801159-TR SPNY801160 SPNY801160-TR SPNY801171 SPNY801172 SPNY801172-TR SPNZ801156 SPNZ801159 SPNZ801159-TR SPNZ801160 SPNZ801160-TR SPNZ801161 SPNZ801171 SPNZ801172
Text Version of Document
KSZ8895MLUB Integrated 5-Port 10/100 Managed Switch Features QoS/CoS Packet Prioritization Support
• Per Port, 802.1p and DiffServ-Based
Advanced Switch Features
• 1/2/4-Queue QoS Prioritization Selection • IEEE 802.1q VLAN Support for up to 128 VLAN Groups (Full-Range 4096 of VLAN IDs) • Programmable Weighted Fair Queuing for Ratio Control • Static MAC Table Supports up to 32 Entries • Re-Mapping of 802.1p Priority Field Per Port • VLAN ID Tag/Untag Options, Per Port Basis Basis • IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis Based on Ingress Port (Egress)
Integrated 5-Port 10/100 Ethernet Switch
• Programmable Rate Limiting at the Ingress and • New Generation Switch with Five MACs and Five Egress on a Per Port Basis PHYs that are Fully Compliant with the IEEE • Jitter-Free Per Packet Based Rate-Limiting Sup- 802.3u Standard port • Non-Blocking Switch Fabric Ensures Fast Packet • Broadcast Storm Protection with Percentage Con- Delivery by Utilizing a 1K MAC Address Lookup trol (Global and Per Port Basis) Table and a Store-and-Forward Architecture • IEEE 802.1d Rapid Spanning Tree Protocol RSTP • On-Chip 64Kbyte Memory for Frame Buffering Support (Not Shared with 1K Unicast Address Table) • Tail Tag Mode (1 Byte Added Before FCS) Sup- • Full-Duplex IEEE 802.3x Flow Control (PAUSE) port at Port 5 to Inform the Processor Which with Force Mode Option Ingress Port Receives the Packet • Half-Duplex Back Pressure Flow Control • 1.4 Gbps High-Performance Memory Bandwidth • HP Auto MDI/MDI-X and IEEE Auto Crossover and Shared Memory Based Switch Fabric with Support Fully Non-Blocking Configuration • Port 5 MAC5 SW5-MII Interface Supports PHY • MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII Mode and MAC Mode Interface • 7-Wire Serial Network Interface (SNI) Support for • Enable/Disable Option for Huge Frame Size (up Legacy MAC to 2000 Bytes Per Frame) • Per Port LED Indicators for Link, Activity, and 10/ • IGMP v1/v2 Snooping (IPv4) Support for Multicast 100 Speed Packet Filtering • Register Port Status Support for Link, Activity, • IPv4/IPv6 QoS Support Full-/Half-Duplex and 10/100 Speed • Support Unknown Unicast/Multicast Address and • LinkMD® Cable Diagnostic Capabilities for Deter- Unknown VID Packet Filtering mining Cable Opens, Shorts, and Length • Self-Address Filtering • On-Chip Terminations and Internal Biasing Tech- nology for Cost Down and Lowest Power Con-
Comprehensive Configuration Register Access
sumption • Serial Management Interface (MDC/MDIO) to All
Switch Monitoring Features
PHYs Registers and SMI Interface (MDC/MDIO) to All Registers • Port Mirroring/Monitoring/Sniffing: Ingress and/or • High-Speed SPI (up to 25 MHz) and I2C Master Egress Traffic to Any Port or MII Interface to all Internal Registers • MIB Counters for Fully Compliant Statistics Gath- • I/O Pins Strapping and EEPROM to Program ering; 34 MIB Counters Per Port Selective Registers in Unmanaged Switch Mode • Loopback Support for MAC, PHY, and Remote • Control Registers Configurable on the Fly (Port- Diagnostic of Failure Priority, 802.1p/d/q, AN…) • Interrupt for the Link Change on Any Ports 2018 Microchip Technology Inc. DS00002680A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
• Per Port, 802.1p and DiffServ-Based
Advanced Switch Features
• 1/2/4-Queue QoS Prioritization Selection • IEEE 802.1q VLAN Support for up to 128 VLAN Groups (Full-Range 4096 of VLAN IDs) • Programmable Weighted Fair Queuing for Ratio Control • Static MAC Table Supports up to 32 Entries • Re-Mapping of 802.1p Priority Field Per Port • VLAN ID Tag/Untag Options, Per Port Basis Basis • IEEE 802.1p/q Tag Insertion or Removal on a Per Port Basis Based on Ingress Port (Egress)
Integrated 5-Port 10/100 Ethernet Switch
• Programmable Rate Limiting at the Ingress and • New Generation Switch with Five MACs and Five Egress on a Per Port Basis PHYs that are Fully Compliant with the IEEE • Jitter-Free Per Packet Based Rate-Limiting Sup- 802.3u Standard port • Non-Blocking Switch Fabric Ensures Fast Packet • Broadcast Storm Protection with Percentage Con- Delivery by Utilizing a 1K MAC Address Lookup trol (Global and Per Port Basis) Table and a Store-and-Forward Architecture • IEEE 802.1d Rapid Spanning Tree Protocol RSTP • On-Chip 64Kbyte Memory for Frame Buffering Support (Not Shared with 1K Unicast Address Table) • Tail Tag Mode (1 Byte Added Before FCS) Sup- • Full-Duplex IEEE 802.3x Flow Control (PAUSE) port at Port 5 to Inform the Processor Which with Force Mode Option Ingress Port Receives the Packet • Half-Duplex Back Pressure Flow Control • 1.4 Gbps High-Performance Memory Bandwidth • HP Auto MDI/MDI-X and IEEE Auto Crossover and Shared Memory Based Switch Fabric with Support Fully Non-Blocking Configuration • Port 5 MAC5 SW5-MII Interface Supports PHY • MII with MAC 5 on Port 5, SW5-MII for MAC 5 MII Mode and MAC Mode Interface • 7-Wire Serial Network Interface (SNI) Support for • Enable/Disable Option for Huge Frame Size (up Legacy MAC to 2000 Bytes Per Frame) • Per Port LED Indicators for Link, Activity, and 10/ • IGMP v1/v2 Snooping (IPv4) Support for Multicast 100 Speed Packet Filtering • Register Port Status Support for Link, Activity, • IPv4/IPv6 QoS Support Full-/Half-Duplex and 10/100 Speed • Support Unknown Unicast/Multicast Address and • LinkMD® Cable Diagnostic Capabilities for Deter- Unknown VID Packet Filtering mining Cable Opens, Shorts, and Length • Self-Address Filtering • On-Chip Terminations and Internal Biasing Tech- nology for Cost Down and Lowest Power Con-
Comprehensive Configuration Register Access
sumption • Serial Management Interface (MDC/MDIO) to All
Switch Monitoring Features
PHYs Registers and SMI Interface (MDC/MDIO) to All Registers • Port Mirroring/Monitoring/Sniffing: Ingress and/or • High-Speed SPI (up to 25 MHz) and I2C Master Egress Traffic to Any Port or MII Interface to all Internal Registers • MIB Counters for Fully Compliant Statistics Gath- • I/O Pins Strapping and EEPROM to Program ering; 34 MIB Counters Per Port Selective Registers in Unmanaged Switch Mode • Loopback Support for MAC, PHY, and Remote • Control Registers Configurable on the Fly (Port- Diagnostic of Failure Priority, 802.1p/d/q, AN…) • Interrupt for the Link Change on Any Ports 2018 Microchip Technology Inc. DS00002680A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 Power 3.3 Power Management 3.4 Switch Core 3.5 Advanced Functionality 3.6 MII Management (MIIM) Interface 3.7 Serial Management Interface (SMI) 4.0 Register Descriptions 4.1 Global Registers 4.2 Port Registers 4.3 Advanced Control Registers 4.4 Static MAC Address Table 4.5 VLAN Table 4.6 Dynamic MAC Address Table 4.7 Management Information Base (MIB) Counters 4.8 MIIM Registers 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings*** 6.0 Electrical Characteristics 7.0 Timing Diagrams 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MII Timing 7.4 SPI Timing 7.5 Auto-Negotiation Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformer, (Note 9-1) 10.0 Package Outline Appendix A: Data Sheet Revision History The Microchip Web Site Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
