Datasheet KSZ8993M (Microchip)
| Manufacturer | Microchip |
| Description | Integrated 3-Port 10/100 Managed Switch with PHYs |
| Pages / Page | 74 / 1 — KSZ8993M. Integrated 3-Port 10/100 Managed Switch with PHYs. Features. • … |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
KSZ8993M. Integrated 3-Port 10/100 Managed Switch with PHYs. Features. • Integrated 3-Port 10/100 Ethernet Switch
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KSZ8993M Integrated 3-Port 10/100 Managed Switch with PHYs Features
- IGMP V1/V2 Snooping Support for Multicast
• Integrated 3-Port 10/100 Ethernet Switch
Packet Filtering - 2nd Generation Switch with Three MACs and - Double-Tagging Support Two PHYs Fully Compliant to IEEE 802.3u
• Switch Management Features
Standard - Port Mirroring/Monitoring/Sniffing: Ingress and/ - Non-Blocking Switch Fabric Ensures Fast or Egress Traffic to Any Port or MII Packet Delivery by Utilizing a 1K MAC Address - Management Information Base Counters for Lookup Table and a Store-and-Forward Archi- Fully Compliant Statistics Gathering, 34 MIB tecture Counters Per Port - Full-Duplex IEEE 802.3x Flow Control (PAUSE) - Loopback Modes for Remote Diagnostic of Fail- with Force Mode Option ure - Half-Duplex Back Pressure Flow Control
• Low Power Dissipation
- Automatic MDI/MDI-X Crossover with Disable - <0.8 Watts (includes PHY transmit drivers) and Enable Option - Full-Chip Hardware Power-Down (Register - 100BASE-FX Support on Port 1 Configuration Not Saved) - MII Interface Supports Both MAC Mode and - Per Port Based Software Power-Save on PHY PHY Mode (Idle Link Detection, Register Configuration Pre- - 7-Wire Serial Network Interface (SNI) Support served) for Legacy MAC - Voltages: Core 1.8V, I/O and Transceiver 3.3V - Comprehensive LED Indicator Support for Link, (Use KSZ8993ML for 3.3V-Only Operation) Activity, Full-/Half-Duplex and 10/100 Speed
• Available in a 128-Pin PQFP Package • Comprehensive Configuration Register Access Applications
- Serial Management Interface (SMI) to All Inter- nal Registers • Universal Solutions - MII Management (MIIM) Interface to PHY Reg- - Broadband Gateway/Firewall/VPN isters - Integrated DSL or Cable Modem Multi-Port - SPI and I2C Interface to all internal registers Router - I/O Pins Strapping and EEPROM to Program - Wireless LAN Access Point + Gateway Selective Registers in Unmanaged Switch - Residential and Enterprise VoIP Gateway/ Mode Phone - Control Registers Configurable on the Fly (Port- - Set-Top/Game Box Priority, 802.1p/d/q, AN, etc.) - Home Networking Expansion
• QoS/CoS Packet Prioritization Support
- Standalone 10/100 Switch - Per Port, 802.1p, and DiffServ-Based - FTTx Customer Premises Equipment - Re-Mapping of 802.1p Priority Field Per Port - Fiber Broadband Gateway Basis • Upgradeable Solutions (Note 1) - Four Priority Levels - Unmanaged Switch with Future Option to
• Advanced Switch Features
Migrate to a Managed Solution - IEEE 802.1q VLAN Support for Up to 16 Groups - Single PHY Alternative with Future Expansion (Full Range of VLAN IDs) Option for Two Ports - VLAN ID Tag/Untag Options, Per Port Basis • Industrial Solutions - IEEE 802.1p/q Tag Insertion or Removal on a - Applications that Require Port Redundancy and Per Port Basis (Egress) Port Monitoring - Programmable Rate Limiting from 0 Mbps to - Sensor Devices in Redundant Ring Topology 100 Mbps at the Ingress and Egress Port, Rate
Note 1:
The cost and time of PCB re-spin. Options for High and Low Priority Per Port Basis - Broadcast Storm Protection with Percent Con- trol (Global and Per Port Basis) - IEEE 802.1d Spanning Tree Protocol Support - Upstream Special Tagging Mode to Inform the Processor which Ingress Port Receives the Packet 2019 Microchip Technology Inc. DS00003066A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
KSZ8993M Integrated 3-Port 10/100 Managed Switch with PHYs Features
- IGMP V1/V2 Snooping Support for Multicast
• Integrated 3-Port 10/100 Ethernet Switch
Packet Filtering - 2nd Generation Switch with Three MACs and - Double-Tagging Support Two PHYs Fully Compliant to IEEE 802.3u
• Switch Management Features
Standard - Port Mirroring/Monitoring/Sniffing: Ingress and/ - Non-Blocking Switch Fabric Ensures Fast or Egress Traffic to Any Port or MII Packet Delivery by Utilizing a 1K MAC Address - Management Information Base Counters for Lookup Table and a Store-and-Forward Archi- Fully Compliant Statistics Gathering, 34 MIB tecture Counters Per Port - Full-Duplex IEEE 802.3x Flow Control (PAUSE) - Loopback Modes for Remote Diagnostic of Fail- with Force Mode Option ure - Half-Duplex Back Pressure Flow Control
• Low Power Dissipation
- Automatic MDI/MDI-X Crossover with Disable - <0.8 Watts (includes PHY transmit drivers) and Enable Option - Full-Chip Hardware Power-Down (Register - 100BASE-FX Support on Port 1 Configuration Not Saved) - MII Interface Supports Both MAC Mode and - Per Port Based Software Power-Save on PHY PHY Mode (Idle Link Detection, Register Configuration Pre- - 7-Wire Serial Network Interface (SNI) Support served) for Legacy MAC - Voltages: Core 1.8V, I/O and Transceiver 3.3V - Comprehensive LED Indicator Support for Link, (Use KSZ8993ML for 3.3V-Only Operation) Activity, Full-/Half-Duplex and 10/100 Speed
• Available in a 128-Pin PQFP Package • Comprehensive Configuration Register Access Applications
- Serial Management Interface (SMI) to All Inter- nal Registers • Universal Solutions - MII Management (MIIM) Interface to PHY Reg- - Broadband Gateway/Firewall/VPN isters - Integrated DSL or Cable Modem Multi-Port - SPI and I2C Interface to all internal registers Router - I/O Pins Strapping and EEPROM to Program - Wireless LAN Access Point + Gateway Selective Registers in Unmanaged Switch - Residential and Enterprise VoIP Gateway/ Mode Phone - Control Registers Configurable on the Fly (Port- - Set-Top/Game Box Priority, 802.1p/d/q, AN, etc.) - Home Networking Expansion
• QoS/CoS Packet Prioritization Support
- Standalone 10/100 Switch - Per Port, 802.1p, and DiffServ-Based - FTTx Customer Premises Equipment - Re-Mapping of 802.1p Priority Field Per Port - Fiber Broadband Gateway Basis • Upgradeable Solutions (Note 1) - Four Priority Levels - Unmanaged Switch with Future Option to
• Advanced Switch Features
Migrate to a Managed Solution - IEEE 802.1q VLAN Support for Up to 16 Groups - Single PHY Alternative with Future Expansion (Full Range of VLAN IDs) Option for Two Ports - VLAN ID Tag/Untag Options, Per Port Basis • Industrial Solutions - IEEE 802.1p/q Tag Insertion or Removal on a - Applications that Require Port Redundancy and Per Port Basis (Egress) Port Monitoring - Programmable Rate Limiting from 0 Mbps to - Sensor Devices in Redundant Ring Topology 100 Mbps at the Ingress and Egress Port, Rate
Note 1:
The cost and time of PCB re-spin. Options for High and Low Priority Per Port Basis - Broadcast Storm Protection with Percent Con- trol (Global and Per Port Basis) - IEEE 802.1d Spanning Tree Protocol Support - Upstream Special Tagging Mode to Inform the Processor which Ingress Port Receives the Packet 2019 Microchip Technology Inc. DS00003066A-page 1 Document Outline 1.0 Introduction 1.1 General Description 2.0 Pin Description and Configuration 3.0 Functional Description 3.1 Physical Layer Transceiver 3.2 MAC and Switch 3.3 Advanced Switch Functions 3.4 Configuration Interface 3.5 Loopback Support 4.0 Register Descriptions 4.1 MII Management (MIIM) Registers 4.2 Register Descriptions 4.3 Register Map: Switch and PHY (8-bit registers) 4.4 Register Descriptions 4.5 Advanced Control Registers (Registers 96-127) 4.6 Static MAC Address Table 4.7 VLAN Table 4.8 Dynamic MAC Address Table 4.9 Management Information Base (MIB) Counters 5.0 Operational Characteristics 5.1 Absolute Maximum Ratings* 5.2 Operating Ratings** 6.0 Electrical Characteristics 7.0 Timing Specifications 7.1 EEPROM Timing 7.2 SNI Timing 7.3 MAC Mode MII Timing 7.4 PHY Mode MII Timing 7.5 SPI Timing 7.6 Reset Timing 8.0 Reset Circuit 9.0 Selection of Isolation Transformers 10.0 Package Outline 10.1 Package Marking Information Appendix A: Data Sheet Revision History The Microchip Website Customer Change Notification Service Customer Support Product Identification System Worldwide Sales and Service
