Datasheet KSZ8993 (Microchip) - 8
| Manufacturer | Microchip |
| Description | 3-Port 10/100 Integrated Switch with PHY and Frame Buffer |
| Pages / Page | 35 / 8 — Pin Number. Pin Name. Type(Note 1). Port. Pin Function. Note 1 |
| File Format / Size | PDF / 231 Kb |
| Document Language | English |
Pin Number. Pin Name. Type(Note 1). Port. Pin Function. Note 1
Model Line for this Datasheet
Text Version of Document
KS8993 Micrel
Pin Number Pin Name Type(Note 1) Port Pin Function
77 MODESEL[3] I Selects LED and test modes 78 MODESEL[2] I Selects LED and test modes 79 MODESEL[1] I Selects LED and test modes 80 MODESEL[0] I Selects LED and test modes 81 TESTEN I Factory test pin - tie low for normal operation 82 SCANEN I Factory test pin - tie low for normal operation 83 RST# I Reset 84 VDD Pwr 2.5V for core digital circuitry 85 GND GND Ground for digital circuitry 86 LED[1][3] O 1 Port 1 LED indicator 3 87 LED[1][2] O 1 Port 1 LED indicator 2 88 LED[1][1] O 1 Port 1 LED indicator 1 89 LED[1][0] O 1 Port 1 LED indicator 0 90 LED[2][3] O 2 Port 2 LED indicator 3 91 LED[2][2] O 2 Port 2 LED indicator 2 92 LED[2][1] O 2 Port 2 LED indicator 1 93 LED[2][0] O 2 Port 2 LED indicator 0 94 VDD_IO Pwr 2.5V or 3.3V for MII interface, LEDs and other digital I/O 95 GND GND Ground for digital circuitry 96 LED[3][3] O 3 Port 3 LED indicator 3 97 LED[3][2] O 3 Port 3 LED indicator 2 98 LED[3][1] O 3 Port 3 LED indicator 1 99 LED[3][0] O 3 Port 3 LED indicator 0 100 PRSV I Priority queue buffer reserve 101 PRSEL[1] I Priority scheme select bit 1 102 PRSEL[0] I Priority scheme select bit 0 103 PBASE2 I Priority base value bit 2 104 PBASE1 I Priority base value bit 1 105 PBASE0 I Priority base value bit 0 106 P3_1PEN I 3 Port 3 802.1p receive priority classification enable 107 P2_1PEN I 2 Port 2 802.1p receive priority classification enable 108 P1_1PEN I 1 Port 1 802.1p receive priority classification enable 109 P3_TXQ2 I 3 Port 3 transmit queue split, priority queueing enable 110 P2_TXQ2 I 2 Port 2 transmit queue split, priority queueing enable 111 P1_TXQ2 I 1 Port 1 transmit queue split, priority queueing enable 112 GND GND Ground for digital circuitry 113 VDD Pwr 2.5V for core digital circuitry 114 P3_PP I 3 Port 3 receive port based priority classification 115 P2_PP I 2 Port 2 receive port based priority classification
Note 1.
Pwr = power supply GND = ground I = input O = output I/O = bi-directional KS8993 8 May 2005
Pin Number Pin Name Type(Note 1) Port Pin Function
77 MODESEL[3] I Selects LED and test modes 78 MODESEL[2] I Selects LED and test modes 79 MODESEL[1] I Selects LED and test modes 80 MODESEL[0] I Selects LED and test modes 81 TESTEN I Factory test pin - tie low for normal operation 82 SCANEN I Factory test pin - tie low for normal operation 83 RST# I Reset 84 VDD Pwr 2.5V for core digital circuitry 85 GND GND Ground for digital circuitry 86 LED[1][3] O 1 Port 1 LED indicator 3 87 LED[1][2] O 1 Port 1 LED indicator 2 88 LED[1][1] O 1 Port 1 LED indicator 1 89 LED[1][0] O 1 Port 1 LED indicator 0 90 LED[2][3] O 2 Port 2 LED indicator 3 91 LED[2][2] O 2 Port 2 LED indicator 2 92 LED[2][1] O 2 Port 2 LED indicator 1 93 LED[2][0] O 2 Port 2 LED indicator 0 94 VDD_IO Pwr 2.5V or 3.3V for MII interface, LEDs and other digital I/O 95 GND GND Ground for digital circuitry 96 LED[3][3] O 3 Port 3 LED indicator 3 97 LED[3][2] O 3 Port 3 LED indicator 2 98 LED[3][1] O 3 Port 3 LED indicator 1 99 LED[3][0] O 3 Port 3 LED indicator 0 100 PRSV I Priority queue buffer reserve 101 PRSEL[1] I Priority scheme select bit 1 102 PRSEL[0] I Priority scheme select bit 0 103 PBASE2 I Priority base value bit 2 104 PBASE1 I Priority base value bit 1 105 PBASE0 I Priority base value bit 0 106 P3_1PEN I 3 Port 3 802.1p receive priority classification enable 107 P2_1PEN I 2 Port 2 802.1p receive priority classification enable 108 P1_1PEN I 1 Port 1 802.1p receive priority classification enable 109 P3_TXQ2 I 3 Port 3 transmit queue split, priority queueing enable 110 P2_TXQ2 I 2 Port 2 transmit queue split, priority queueing enable 111 P1_TXQ2 I 1 Port 1 transmit queue split, priority queueing enable 112 GND GND Ground for digital circuitry 113 VDD Pwr 2.5V for core digital circuitry 114 P3_PP I 3 Port 3 receive port based priority classification 115 P2_PP I 2 Port 2 receive port based priority classification
Note 1.
Pwr = power supply GND = ground I = input O = output I/O = bi-directional KS8993 8 May 2005
