Datasheet AD7293 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 12-Bit Power Amplifier Current Controller with ADC, DACs, Temperature and Current Sensors |
| Pages / Page | 79 / 9 — Data Sheet. AD7293. CURRENT SENSOR. Table 4. Parameter. Min. Typ. Max. … |
| Revision | D |
| File Format / Size | PDF / 1.6 Mb |
| Document Language | English |
Data Sheet. AD7293. CURRENT SENSOR. Table 4. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments. CLOSED-LOOP SPECIFICATIONS
Model Line for this Datasheet
Text Version of Document
link to page 42 link to page 20 link to page 44 link to page 58 link to page 58 link to page 29 link to page 29
Data Sheet AD7293 CURRENT SENSOR
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AVSS = −5 V, PAVDD = 5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, gain = 6.25, unless otherwise noted.
Table 4. Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT SENSE RSx+ = AVDD to AVSS + 60 V Common-Mode Input Voltage Range 4 60 V AVSS = 0 V 4 55 V AVSS = −5 V Differential Input Voltage Range −200 +200 mV Gain = 6.25, for gain settings, see Table 44 Gain Error ±0.1 ±0.7 % Gain Error Temperature Coefficient −16 ppm/°C Offset Error (Referred to Input, RTI) ±200 µV Offset Error Drift 1 µV/°C DC Common-Mode Rejection 100 140 dB RSx+1 Pin Input Current 105 µA RSx−1 Pin Input Current 10 nA Differential Input Resistance2 700 kΩ 1 Where x is 0, 1, 2, or 3. 2 Guaranteed by design and characterization; not production tested.
CLOSED-LOOP SPECIFICATIONS
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AVSS = −5 V, PAVDD = 5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted. Power amplifier transconductance = 1 S to 5 S, and external gate filter time constant (τG) = 5 µs to 50 µs.
Table 5. Parameter Min Typ Max Unit Test Conditions/Comments
NORMAL OPERATION1, 2 Setpoint Resolution 12 Bits Equivalent to 200 mV/4096 = 49 µV at the current sense input Sense Resistor Voltage Range 0 200 mV Setpoint Gain Error ±0.5 % Setpoint Offset Error (RTI) ±100 µV Referred to current sense input; see Figure 31 Integrator Time Constant3 840 µs Programmable; see Table 50 Closed-Loop Update Rate3 59.6 kHz Capacitive Load Stability 1 µF 5 Ω series resistance Closed-Loop to Clamp Settling Time 1 µs Within ±10% Bipolar Closed-Loop Output Range AVSS AVDD V See the Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) section Integrator Programmable Voltage Limit Resolution 2.5 mV See the Closed-Loop Integrator Programmable Voltage Limit section START SEQUENCING PA_ON CONTROL2 PA_ON Pin Output Voltage AGND PAVDD V PA_ON Off State Enable 500 µs Measured from AVSS failure event, CL = 1 nF 500 µs Measured from SLEEP0 or SLEEP1 pin, 0 to 1 transition, CL = 1 nF PA_ON On State Enable 500 µs Measured from SLEEP1 to SLEEP0 transition, CL = 1 nF PA_ON Short-Circuit Current ±10 mA PA_ON Resistance 250 Ω AVDD/AVSS ALARM AVDD Alarm Threshold 3.2 3.6 3.9 V AVSS Alarm Threshold −3.8 −4.1 −4.4 V 1 Power amplifier characteristic dependent. 2 Guaranteed by design and characterization; not production tested. 3 Expressed as a function of the internal oscillator frequency. Rev. D | Page 9 of 79 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ADC DAC TEMPERATURE SENSOR CURRENT SENSOR CLOSED-LOOP SPECIFICATIONS GENERAL TIMING CHARACTERISTICS SPI Serial Interface Asynchronous Inputs Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Pseudo Differential Mode CURRENT SENSOR Choosing the External Sense Resistor (RSENSE) TEMPERATURE SENSOR INTERNAL CHANNEL MONITORING DAC OPERATION Bipolar DACs Unipolar DACs DAC Enabling and Clamping Software Clamping: Internal ALERT0 Routing PMOS Drain Switch Control REFERENCE VDRIVE FEATURE OPEN-LOOP MODE CLOSED-LOOP MODE Adjustable Closed-Loop Setpoint Ramp Time Fast Ramp Feature Closed-Loop Sequencing Closed-Loop Integrator Programmable Voltage Limit Closed-Loop Range Upper Voltage Limit DIGITAL INPUT/OUTPUT REGISTERS LOAD DAC (LDAC PIN) Instantaneous DAC Updating (Asynchronous) Deferred DAC Updating (Synchronous) ALERTS AND LIMITS ALERTx Pins Software Alerts Page GPIO0 to GPIO3 Routing to ALERT1 AVDD AND AVSS ALARM MAXIMUM AND MINIMUM PAGES HYSTERESIS REGISTER SETTINGS REGISTERS COMMON TO ALL PAGES No Op Register (Register 0x00) Page Select Pointer Register (Register 0x01) Conversion Command (Register 0x02) Result Register (Register 0x03) DAC Enable Register (Register 0x04) GPIO Register (Register 0x05) Device ID Register (Register 0x0C) Software Reset Register (Register 0x0F) RESULT 0/DAC INPUT (PAGE 0x00) Voltage Input (VINx) Result Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEINT and TSENSEDx) Result Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Result Registers (Register 0x28 to Register 0x2B) DAC Input (UNI-VOUTx and BI-VOUTx) Registers (Register 0x30 to Register 0x37) RESULT 1 (PAGE 0x01) Voltage Supply Monitor Result Registers (Register 0x10 to Register 0x13) Bipolar DAC Internal Monitor Result (BI-VOUT0MON to BI-VOUT3MON) Registers (Register 0x14 to Register 0x17) RSx+MON Result Registers (Register 0x28 to Register 0x2B) CONFIGURATION (PAGE 0x02) Digital Output Enable Register (Register 0x11) Digital Input/Output Function Register (Register 0x12) Digital Functional Polarity Register (Register 0x13) General Register (Register 0x14) VINx Range x Registers (Register 0x15 and Register 0x16) VINx Differential/Single-Ended Enable Register (Register 0x17) VINx Filter Register (Register 0x18) VINx Background Enable Register (Register 0x19) Conversion Delay Register (Register 0x1A) Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B) Current Sensor (ISENSEx) Background Enable Register (Register 0x1C) Current Sensor (ISENSEx) Gain Register (Register 0x1D) DAC Snooze/SLEEP0 Pin Register (Register 0x1F) DAC Snooze/SLEEP1 Pin Register (Register 0x20) RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23) Integrator Limit and Closed-Loop Control Register (Register 0x28) PA_ON Control Register (Register 0x29) Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F) SEQUENCE (PAGE 0x03) Voltage Input (VINx) Sequence Register (Register 0x10) Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx) Sequence Register (Register 0x11) RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12) HIGH LIMIT 0 (PAGE 0x04) VINx High Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) High Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) High Limit Registers (Register 0x28 to Register 0x2B) HIGH LIMIT 1 (PAGE 0x05) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) RSx+MON High Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 0 (PAGE 0x06) VINx Low Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Low Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Low Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 1 (PAGE 0x07) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers (Register 0x14 to Register 0x17) RSx+MON Low Limit Registers (Register 0x28 to Register 0x2B) HYSTERESIS 0 (PAGE 0x08) VINx Hysteresis Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Hysteresis Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Hysteresis Registers (Register 0x28 to Register 0x2B) HYSTERESIS 1 (PAGE 0x09) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Hysteresis Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers (Register 0x14 to Register 0x17) RSx+MON Hysteresis Registers (Register 0x28 to Register 0x2B) MINIMUM 0 (PAGE 0x0A) VINx Minimum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Minimum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Minimum Registers (Register 0x28 to Register 0x2B) MINIMUM 1 (PAGE 0x0B) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Minimum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Minimum Registers (Register 0x14 to Register 0x17) RSx+MON Minimum Registers (Register 0x28 to Register 0x2B) MAXIMUM 0 (PAGE 0x0C) VINx Maximum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Maximum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Maximum Registers (Register 0x28 to Register 0x2B) MAXIMUM 1 (PAGE 0x0D) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Maximum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Maximum Registers (Register 0x14 to Register 0x17) RSx+MON Maximum Registers (Register 0x28 to Register 0x2B) OFFSET 0 (PAGE 0x0E) VINx Offset Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Offset Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Offset Registers (Register 0x28 to Register 0x2B) Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30 to Register 0x33) Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) OFFSET 1 (PAGE 0x0F) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14 to Register 0x17) RSx+MON Offset Registers (Register 0x28 to Register 0x2B) ALERT (PAGE 0x10) Alert Summary (ALERTSUM) Register (Register 0x10) VINx Alert Register (Register 0x12) Temperature Sensor (TSENSEx) Alert Register (Register 0x14) Current Sensor (ISENSEx) Alert Register (Register 0x15) Supply and BI-VOUTxMON Alert Register (Register 0x18) RSx+MON Alert Register (Register 0x19) INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A) ALERT0 PIN ROUTING (PAGE 0x11) VINx ALERT0 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT0 Register (Register 0x14) Current Sensor (ISENSEx) ALERT0 Register (Register 0x15) Supply and BI-VOUTxMON ALERT0 Register (Register 0x18) RSx+MON ALERT0 Register (Register 0x19) INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A) ALERT1 PIN ROUTING (PAGE 0x12) VINx ALERT1 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT1 Register (Register 0x14) Current Sensor (ISENSEx) ALERT1 Register (Register 0x15) Supply and BI-VOUTxMON ALERT1 Register (Register 0x18) RSx+MON ALERT1 Register (Register 0x19) INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A) SERIAL PORT INTERFACE INTERFACE PROTOCOL MODES OF OPERTION Background Mode (BG) Command Mode Current Sensor and Temperature Sensor Conversions Conversion Timing Current Sense and Temperature Sense Channel Integration Time Conversion and Integration Timing Example 1 Conversion and Integration Timing Example 2 Digital Filtering APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER CONTROL DEPLETION MODE AMPLIFIER BIASING AND PROTECTION LOOP COMPONENT SELECTION OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD7293 CURRENT SENSOR
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AVSS = −5 V, PAVDD = 5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, gain = 6.25, unless otherwise noted.
Table 4. Parameter Min Typ Max Unit Test Conditions/Comments
CURRENT SENSE RSx+ = AVDD to AVSS + 60 V Common-Mode Input Voltage Range 4 60 V AVSS = 0 V 4 55 V AVSS = −5 V Differential Input Voltage Range −200 +200 mV Gain = 6.25, for gain settings, see Table 44 Gain Error ±0.1 ±0.7 % Gain Error Temperature Coefficient −16 ppm/°C Offset Error (Referred to Input, RTI) ±200 µV Offset Error Drift 1 µV/°C DC Common-Mode Rejection 100 140 dB RSx+1 Pin Input Current 105 µA RSx−1 Pin Input Current 10 nA Differential Input Resistance2 700 kΩ 1 Where x is 0, 1, 2, or 3. 2 Guaranteed by design and characterization; not production tested.
CLOSED-LOOP SPECIFICATIONS
AVDD, DVDD, DACVDD-BI = 4.5 V to 5.5 V (connect AVDD and DACVDD-BI to the same potential), DACVDD-UNI = 5 V, AVSS = −5 V, PAVDD = 5 V, AGND = DGND = 0 V, VREFIN = 2.5 V internal or external; VDRIVE = 1.7 V to 5.5 V; TA = −40°C to +125°C, unless otherwise noted. Power amplifier transconductance = 1 S to 5 S, and external gate filter time constant (τG) = 5 µs to 50 µs.
Table 5. Parameter Min Typ Max Unit Test Conditions/Comments
NORMAL OPERATION1, 2 Setpoint Resolution 12 Bits Equivalent to 200 mV/4096 = 49 µV at the current sense input Sense Resistor Voltage Range 0 200 mV Setpoint Gain Error ±0.5 % Setpoint Offset Error (RTI) ±100 µV Referred to current sense input; see Figure 31 Integrator Time Constant3 840 µs Programmable; see Table 50 Closed-Loop Update Rate3 59.6 kHz Capacitive Load Stability 1 µF 5 Ω series resistance Closed-Loop to Clamp Settling Time 1 µs Within ±10% Bipolar Closed-Loop Output Range AVSS AVDD V See the Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) section Integrator Programmable Voltage Limit Resolution 2.5 mV See the Closed-Loop Integrator Programmable Voltage Limit section START SEQUENCING PA_ON CONTROL2 PA_ON Pin Output Voltage AGND PAVDD V PA_ON Off State Enable 500 µs Measured from AVSS failure event, CL = 1 nF 500 µs Measured from SLEEP0 or SLEEP1 pin, 0 to 1 transition, CL = 1 nF PA_ON On State Enable 500 µs Measured from SLEEP1 to SLEEP0 transition, CL = 1 nF PA_ON Short-Circuit Current ±10 mA PA_ON Resistance 250 Ω AVDD/AVSS ALARM AVDD Alarm Threshold 3.2 3.6 3.9 V AVSS Alarm Threshold −3.8 −4.1 −4.4 V 1 Power amplifier characteristic dependent. 2 Guaranteed by design and characterization; not production tested. 3 Expressed as a function of the internal oscillator frequency. Rev. D | Page 9 of 79 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAMS SPECIFICATIONS ADC DAC TEMPERATURE SENSOR CURRENT SENSOR CLOSED-LOOP SPECIFICATIONS GENERAL TIMING CHARACTERISTICS SPI Serial Interface Asynchronous Inputs Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ANALOG-TO-DIGITAL CONVERTER (ADC) OVERVIEW ADC TRANSFER FUNCTIONS ANALOG INPUTS Single-Ended Mode Differential Mode Pseudo Differential Mode CURRENT SENSOR Choosing the External Sense Resistor (RSENSE) TEMPERATURE SENSOR INTERNAL CHANNEL MONITORING DAC OPERATION Bipolar DACs Unipolar DACs DAC Enabling and Clamping Software Clamping: Internal ALERT0 Routing PMOS Drain Switch Control REFERENCE VDRIVE FEATURE OPEN-LOOP MODE CLOSED-LOOP MODE Adjustable Closed-Loop Setpoint Ramp Time Fast Ramp Feature Closed-Loop Sequencing Closed-Loop Integrator Programmable Voltage Limit Closed-Loop Range Upper Voltage Limit DIGITAL INPUT/OUTPUT REGISTERS LOAD DAC (LDAC PIN) Instantaneous DAC Updating (Asynchronous) Deferred DAC Updating (Synchronous) ALERTS AND LIMITS ALERTx Pins Software Alerts Page GPIO0 to GPIO3 Routing to ALERT1 AVDD AND AVSS ALARM MAXIMUM AND MINIMUM PAGES HYSTERESIS REGISTER SETTINGS REGISTERS COMMON TO ALL PAGES No Op Register (Register 0x00) Page Select Pointer Register (Register 0x01) Conversion Command (Register 0x02) Result Register (Register 0x03) DAC Enable Register (Register 0x04) GPIO Register (Register 0x05) Device ID Register (Register 0x0C) Software Reset Register (Register 0x0F) RESULT 0/DAC INPUT (PAGE 0x00) Voltage Input (VINx) Result Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEINT and TSENSEDx) Result Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Result Registers (Register 0x28 to Register 0x2B) DAC Input (UNI-VOUTx and BI-VOUTx) Registers (Register 0x30 to Register 0x37) RESULT 1 (PAGE 0x01) Voltage Supply Monitor Result Registers (Register 0x10 to Register 0x13) Bipolar DAC Internal Monitor Result (BI-VOUT0MON to BI-VOUT3MON) Registers (Register 0x14 to Register 0x17) RSx+MON Result Registers (Register 0x28 to Register 0x2B) CONFIGURATION (PAGE 0x02) Digital Output Enable Register (Register 0x11) Digital Input/Output Function Register (Register 0x12) Digital Functional Polarity Register (Register 0x13) General Register (Register 0x14) VINx Range x Registers (Register 0x15 and Register 0x16) VINx Differential/Single-Ended Enable Register (Register 0x17) VINx Filter Register (Register 0x18) VINx Background Enable Register (Register 0x19) Conversion Delay Register (Register 0x1A) Temperature Sensor (TSENSEx) Background Enable Register (Register 0x1B) Current Sensor (ISENSEx) Background Enable Register (Register 0x1C) Current Sensor (ISENSEx) Gain Register (Register 0x1D) DAC Snooze/SLEEP0 Pin Register (Register 0x1F) DAC Snooze/SLEEP1 Pin Register (Register 0x20) RSx+MON, Supply Monitor, BI-VOUTx Background Enable Register (Register 0x23) Integrator Limit and Closed-Loop Control Register (Register 0x28) PA_ON Control Register (Register 0x29) Ramp Time 0 to Ramp Time 3 Registers (Register 0x2A to Register 0x2D) Closed-Loop Fast Ramp and Integrator Time Constant Register (Register 0x2E) Integrator Limit Active Status (INTLIMITx) and AVSS/AVDD Alarm Mask Register (Register 0x2F) SEQUENCE (PAGE 0x03) Voltage Input (VINx) Sequence Register (Register 0x10) Current Sensor (ISENSEx) and Temperature Sensor (TSENSEx) Sequence Register (Register 0x11) RSx+MON, Supply Monitor, and BI-VOUTx Monitor Sequence Register (Register 0x12) HIGH LIMIT 0 (PAGE 0x04) VINx High Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) High Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) High Limit Registers (Register 0x28 to Register 0x2B) HIGH LIMIT 1 (PAGE 0x05) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI) and AVSS High Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON High Limit Registers (Register 0x14 to Register 0x17) RSx+MON High Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 0 (PAGE 0x06) VINx Low Limit Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Low Limit Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Low Limit Registers (Register 0x28 to Register 0x2B) LOW LIMIT 1 (PAGE 0x07) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Low Limit Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Low Limit Registers (Register 0x14 to Register 0x17) RSx+MON Low Limit Registers (Register 0x28 to Register 0x2B) HYSTERESIS 0 (PAGE 0x08) VINx Hysteresis Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Hysteresis Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Hysteresis Registers (Register 0x28 to Register 0x2B) HYSTERESIS 1 (PAGE 0x09) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Hysteresis Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Hysteresis Registers (Register 0x14 to Register 0x17) RSx+MON Hysteresis Registers (Register 0x28 to Register 0x2B) MINIMUM 0 (PAGE 0x0A) VINx Minimum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Minimum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Minimum Registers (Register 0x28 to Register 0x2B) MINIMUM 1 (PAGE 0x0B) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Minimum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Minimum Registers (Register 0x14 to Register 0x17) RSx+MON Minimum Registers (Register 0x28 to Register 0x2B) MAXIMUM 0 (PAGE 0x0C) VINx Maximum Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Maximum Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Maximum Registers (Register 0x28 to Register 0x2B) MAXIMUM 1 (PAGE 0x0D) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Maximum Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3MON Maximum Registers (Register 0x14 to Register 0x17) RSx+MON Maximum Registers (Register 0x28 to Register 0x2B) OFFSET 0 (PAGE 0x0E) VINx Offset Registers (Register 0x10 to Register 0x13) Temperature Sensor (TSENSEx) Offset Registers (Register 0x20 to Register 0x22) Current Sensor (ISENSEx) Offset Registers (Register 0x28 to Register 0x2B) Unipolar DAC (UNI-VOUTx) Offset Registers (Register 0x30 to Register 0x33) Bipolar DAC (BI-VOUTx) Offset Registers (Register 0x34 to Register 0x37) OFFSET 1 (PAGE 0x0F) AVDD, DAC Supply (DACVDD-UNI/DACVDD-BI), and AVSS Offset Registers (Register 0x10 to Register 0x13) BI-VOUT0MON to BI-VOUT3 MON Offset Registers (Register 0x14 to Register 0x17) RSx+MON Offset Registers (Register 0x28 to Register 0x2B) ALERT (PAGE 0x10) Alert Summary (ALERTSUM) Register (Register 0x10) VINx Alert Register (Register 0x12) Temperature Sensor (TSENSEx) Alert Register (Register 0x14) Current Sensor (ISENSEx) Alert Register (Register 0x15) Supply and BI-VOUTxMON Alert Register (Register 0x18) RSx+MON Alert Register (Register 0x19) INTLIMITx and AVSS/AVDD Alert Register (Register 0x1A) ALERT0 PIN ROUTING (PAGE 0x11) VINx ALERT0 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT0 Register (Register 0x14) Current Sensor (ISENSEx) ALERT0 Register (Register 0x15) Supply and BI-VOUTxMON ALERT0 Register (Register 0x18) RSx+MON ALERT0 Register (Register 0x19) INTLIMITx and AVss/AVDD ALERT0 Register (Register 0x1A) ALERT1 PIN ROUTING (PAGE 0x12) VINx ALERT1 Register (Register 0x12) Temperature Sensor (TSENSEx) ALERT1 Register (Register 0x14) Current Sensor (ISENSEx) ALERT1 Register (Register 0x15) Supply and BI-VOUTxMON ALERT1 Register (Register 0x18) RSx+MON ALERT1 Register (Register 0x19) INTLIMITx and AVSS/AVDD ALERT1 Register (Register 0x1A) SERIAL PORT INTERFACE INTERFACE PROTOCOL MODES OF OPERTION Background Mode (BG) Command Mode Current Sensor and Temperature Sensor Conversions Conversion Timing Current Sense and Temperature Sense Channel Integration Time Conversion and Integration Timing Example 1 Conversion and Integration Timing Example 2 Digital Filtering APPLICATIONS INFORMATION BASE STATION POWER AMPLIFIER CONTROL DEPLETION MODE AMPLIFIER BIASING AND PROTECTION LOOP COMPONENT SELECTION OUTLINE DIMENSIONS ORDERING GUIDE
