Datasheet AD7294-2 (Analog Devices) - 8
| Manufacturer | Analog Devices |
| Description | 12-Bit Monitor and Control System with Multichannel ADC, DACs, Temperature Sensor, and Current Sense |
| Pages / Page | 44 / 8 — AD7294-2. Data Sheet. TIMING CHARACTERISTICS I2C Serial Interface. Table … |
| File Format / Size | PDF / 960 Kb |
| Document Language | English |
AD7294-2. Data Sheet. TIMING CHARACTERISTICS I2C Serial Interface. Table 4. Parameter. Limit at TMIN, TMAX. Unit. Symbol. Description
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AD7294-2 Data Sheet TIMING CHARACTERISTICS I2C Serial Interface
AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted.
Table 4. Parameter
1
Limit at TMIN, TMAX Unit Symbol Description
fSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min tHIGH SCL high time t3 1.3 µs min tLOW SCL low time t4 0.6 µs min tHD,STA Start/repeated start condition hold time t5 100 ns min tSU,DAT Data setup time t6 0.9 µs max tHD,DAT Data hold time 0 µs min tHD,DAT Data hold time t7 0.6 µs min tSU,STA Setup time for repeated start t8 0.6 µs min tSU,STO Stop condition setup time t9 1.3 µs min tBUF Bus free time between a stop and a start condition t 2 10 300 ns max tR Rise time of SCL and SDA when receiving 0 ns min tR Rise time of SCL and SDA when receiving (CMOS compatible) t 2 11 300 ns max tF Fall time of SDA when transmitting 20 × (VDRIVE/5.5 V) ns min tF Fall time of SCL and SDA when transmitting 0 ns min tF Fall time of SDA when receiving (CMOS compatible) 300 ns max tF Fall time of SCL and SDA when receiving C 3 b 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 tR and tF are measured between 0.3 VDD and 0.7 VDD. 3 Cb is the total capacitance in pF of one bus line.
Timing and Circuit Diagrams SDA t9 t3 t t 10 11 t4 SCL t t t t 4 6 2 1 t8 t5 t7 START REPEATED STOP
002
CONDITION START CONDITION CONDITION
10936- Figure 2. I2C-Compatible Serial Interface Timing Diagram
200µA IOL TO OUTPUT PIN VOH (MIN) OR C V L OL (MAX) 50pF
003
200µA IOH
10936- Figure 3. Load Circuit for Digital Output Rev. 0 | Page 8 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide
AD7294-2 Data Sheet TIMING CHARACTERISTICS I2C Serial Interface
AVDD = 4.5 V to 5.5 V, AGND1 to AGND7 = DGND = 0 V, internal or external 2.5 V reference; VDRIVE = 2.7 V to 5.5 V; VPPx = AVDD to 59.4 V; DAC OUTV+ AB and DAC OUTV+ CD = 4.5 V to 16.5 V; OFFSET IN x is floating, therefore, DAC output span = 0 V to 5 V; TA = −40°C to +105°C, unless otherwise noted.
Table 4. Parameter
1
Limit at TMIN, TMAX Unit Symbol Description
fSCL 400 kHz max SCL clock frequency t1 2.5 µs min SCL cycle time t2 0.6 µs min tHIGH SCL high time t3 1.3 µs min tLOW SCL low time t4 0.6 µs min tHD,STA Start/repeated start condition hold time t5 100 ns min tSU,DAT Data setup time t6 0.9 µs max tHD,DAT Data hold time 0 µs min tHD,DAT Data hold time t7 0.6 µs min tSU,STA Setup time for repeated start t8 0.6 µs min tSU,STO Stop condition setup time t9 1.3 µs min tBUF Bus free time between a stop and a start condition t 2 10 300 ns max tR Rise time of SCL and SDA when receiving 0 ns min tR Rise time of SCL and SDA when receiving (CMOS compatible) t 2 11 300 ns max tF Fall time of SDA when transmitting 20 × (VDRIVE/5.5 V) ns min tF Fall time of SCL and SDA when transmitting 0 ns min tF Fall time of SDA when receiving (CMOS compatible) 300 ns max tF Fall time of SCL and SDA when receiving C 3 b 400 pF max Capacitive load for each bus line 1 See Figure 2. 2 tR and tF are measured between 0.3 VDD and 0.7 VDD. 3 Cb is the total capacitance in pF of one bus line.
Timing and Circuit Diagrams SDA t9 t3 t t 10 11 t4 SCL t t t t 4 6 2 1 t8 t5 t7 START REPEATED STOP
002
CONDITION START CONDITION CONDITION
10936- Figure 2. I2C-Compatible Serial Interface Timing Diagram
200µA IOL TO OUTPUT PIN VOH (MIN) OR C V L OL (MAX) 50pF
003
200µA IOH
10936- Figure 3. Load Circuit for Digital Output Rev. 0 | Page 8 of 44 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications DAC Specifications ADC Specifications General Specifications Timing Characteristics I2C Serial Interface Timing and Circuit Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology DAC Terminology ADC Terminology Theory of Operation ADC Overview ADC Transfer Functions Analog Inputs Single-Ended Mode Differential Mode Driving Differential Inputs Using an Op Amp Pair Pseudo Differential Mode Current Sensor Choosing RSENSE Current Sense Filtering Kelvin Sense Resistor Connection Analog Comparator Loop Temperature Sensor Remote Sensing Diode Ideality Factor Base Emitter Voltage hFE Variation Series Resistance Cancellation DAC Operation Resistor String Output Amplifiers ADC and DAC Reference VDRIVE Feature Register Settings Address Pointer Register Command Register ADC Result Register ADC Channel Allocation TSENSE1 and TSENSE2 Result Registers TSENSEINT Result Register Temperature Value Format DACA, DACB, DACC, and DACD Value Registers Alert Status Register A, Alert Status Register B, and Alert Status Register C Channel Sequence Register Configuration Register Sample Delay and Bit Trial Delay Power-Down Register DATALOW and DATAHIGH Registers VIN0 to VIN3 Channels TSENSE1, TSENSE2, and TSENSEINT Channels Hysteresis Registers Remote Channel TSENSE1 and TSENSE2 Offset Registers I2C Interface General I2C Timing Serial Bus Address Byte Interface Protocol Writing a Single Byte of Data to an 8-Bit Register Writing Two Bytes of Data to a 16-Bit Register Writing to Multiple Registers Reading Data from an 8-Bit Register Reading Two Bytes of Data from a 16-Bit Register Modes of Operation Command Mode Autocycle Mode Alerts and Limits Theory ALERT_FLAG Bit Alert Status Registers DATALOW and DATAHIGH Monitoring Features Hysteresis Using the Limit Registers to Store Minimum/Maximum Conversion Results Applications Information Base Station Power Amplifier Monitor and Control Gain Control of Power Amplifier Outline Dimensions Ordering Guide
