Datasheet ADuCM3027, ADuCM3029 (Analog Devices) - 8

ADuCM3027 /ADuCM3029 Data Sheet SYSTEM CLOCKS External Crystal Oscillator Specifications Table 8.
Parameter Symbol Min Typ Max Unit Test Conditions/Comments LOW FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (LFXTAL) Frequency fLFXTAL 32,768 Hz External Capacitance from CLFXTAL 6 10 pF External capacitors on SYS_LFXTAL_IN SYS_LFXTAL_IN Pin to Ground and and SYS_LFXTAL_OUT pins must be from SYS_LFXTAL_OUT Pin to Ground selected considering the printed circuit board (PCB) trace capacitance due to routing Crystal Equivalent Series Resistance ESRLFXTAL 30 kΩ HIGH FREQUENCY EXTERNAL CRYSTAL OSCILLATOR (HFXTAL) Frequency fHFXTAL 26 MHz External Capacitance from CHFXTAL 20 pF External capacitors on SYS_HFXTAL_IN SYS_HFXTAL_IN Pin to Ground and and SYS_HFXTAL_OUT pins must be from SYS_HFXTAL_OUT Pin to Ground selected considering the PCB trace capacitance due to routing Crystal Equivalent Series Resistance ESRHFXTAL 50 Ω
On-Chip RC Oscillator Specifications Table 9. Parameter Symbol Min Typ Max Unit
LOW FREQUENCY RC OSCILLATOR (LFOSC) Frequency fLFOSC 30,800 32,768 34,407 Hz HIGH FREQUENCY RC OSCILLATOR (HFOSC) Frequency fHFOSC 25.09 26 26.728 MHz
System Clocks and PLL Specifications Table 10. Parameter Symbol Min Typ Max Unit
PLL SPECIFICATIONS PLL Input Clock Frequency1 fPLLIN 16 26 MHz PLL Output Clock Frequency2, 3 fPLLOUT 16 60 MHz System Peripheral Clock (PCLK) Frequency fPCLK 0.8125 26 MHz Advanced High Performance Bus Clock (HCLK) Frequency fHCLK 0.8125 26 MHz 1 The input to the PLL can come from either the high frequency external crystal (HFXTAL), SYS_CLKIN pin or from the high frequency internal RC oscillator (HFOSC). 2 For the maximum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 16, PLL_DIV2 = 1 for PLL input clock = 26 MHz; and PLL_MSEL = 13, PLL_NSEL = 26, PLL_DIV2 = 1 for PLL input clock = 16 MHz. 3 For the minimum value, the recommended settings are PLL_MSEL = 13, PLL_NSEL = 30, PLL_DIV2 = 0 for PLL input clock = 26 MHz; and PLL_MSEL = 8, PLL_NSEL = 30, PLL_DIV2 = 0 for 16 MHz. Rev. B | Page 8 of 39 Document Outline Features Applications Functional Block Diagram Revision History General Description Product Highlights Specifications Operating Conditions and Electrical Characteristics Embedded Flash Specifications Power Supply Current Specifications Active Mode Flexi Mode Deep Sleep Modes—VBAT = 3.0 V ADC Specifications System Clocks External Crystal Oscillator Specifications On-Chip RC Oscillator Specifications System Clocks and PLL Specifications Timing Specifications Reset Timing Serial Ports Timing SPI Timing I2C Specifications General-Purpose Port Timing RTC1 (FLEX_RTC) Specifications Timer Pulse-Width Modulation (PWM) Output Cycle Timing Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation ARM Cortex-M3 Processor ARM Cortex-M3 Memory Subsystem Code Region SRAM Region System Region Memory Architecture SRAM Region MMRs (Peripheral Control and Status) Flash Memory Cache Controller System and Integration Features Reset Booting Power Management Power Modes Active Mode Flexi Mode Hibernate Mode Shutdown Mode Security Features Cryptographic Accelerator True Random Number Generator (TRNG) Reliability and Robustness Features ECC Enabled Flash Memory Multiparity Bit Protected SRAM Software Watchdog Cyclic Redundancy Check (CRC) Accelerator Programmable GPIOs Timers General-Purpose Timers Watchdog Timer (WDT) Analog-to-Digital Converter (ADC) Subsystem Clocking Beeper Driver Debug Capability On-Chip Peripheral Features Serial Ports (SPORT) SPI Ports UART Port I2C Development Support Documentation Hardware Software Additional Information Reference Designs MCU Test Conditions Driver Types EEMBC ULPMark™-CP Score GPIO Multiplexing Applications Information About ADuCM3027/ADuCM3029 Silicon Anomalies Functionality Issues Outline Dimensions Ordering Guide