Datasheet LTM4668A (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Quad DC/DC µModule Regulator with Configurable 1.2A Output Array |
| Pages / Page | 24 / 7 — PIN FUNCTIONS VIN (A4, B4, F4, G4):. VOUT1 (A1, B1), VOUT2 (A7, B7), … |
| Revision | A |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
PIN FUNCTIONS VIN (A4, B4, F4, G4):. VOUT1 (A1, B1), VOUT2 (A7, B7), VOUT3 (F7, G7), VOUT4 INTVCC (C4):. (F1, G1):
Model Line for this Datasheet
Text Version of Document
link to page 10 link to page 10 LTM4668A
PIN FUNCTIONS VIN (A4, B4, F4, G4):
Power Input Pins connect to the 400mA peak current clamp. Tie MODE/SYNC to GND for drain of the internal top MOSFET for each switching mode pulse-skipping operation, and tie MODE/SYNC to a volt- regulator channel and the internal 5V regulator for the age between 1V and INTVCC – 1.2V for forced continuous control circuitry. Apply input voltages between these mode. Furthermore, connecting this pin to an external pins and GND pins. Recommend placing input decou- clock will synchronize the switch clock to the external pling capacitance directly between each of VIN pins and clock and put the part in forced continuous mode. Do GND pins. not float this pin.
VOUT1 (A1, B1), VOUT2 (A7, B7), VOUT3 (F7, G7), VOUT4 INTVCC (C4):
Internal 5V Regulator Output. The internal
(F1, G1):
Power Output Pins of each switching mode power drivers and control circuits are powered from this regulator channel. Apply output load between these pins voltage. Decouple each pin to GND with a minimum of and GND pins. Recommend placing output decoupling 2.2µF local low ESR ceramic capacitor. INTVCC only starts capacitance directly between these pins and GND pins. up if at least one of the RUN pins is high. See the Applications Information section for paralleling
RUN1 (C3), RUN2 (C5), RUN3 (E5), RUN4 (E3):
Run outputs. Control Input of each switching mode regulator channel.
GND (A2–A3, A5–A6, B2–B3, B5–B6, C2, C6, D3–D5,
Enable regulator operation by tying the specific RUN pin
E2, E6, F2–F3, F5–F6, G2–G3, G5–G6):
Power Ground above 1V. Tying it below 0.35V shuts down the specific Pins for both Input and Output Returns. Use large PCB regulator channel. copper areas to connect all GND together.
FB1 (C1), FB2 (C7), FB3 (E7), FB4 (E1):
The Negative
PGOOD1 (D2), PGOOD2 (D6), PGOOD3 (D7), PGOOD4
Input of the Error Amplifier for each switching mode regu-
(D1):
Output Power Good with Open-Drain Logic of each lator channel. Internally, this pin is connected to VOUT of switching mode regulator channel. PGOOD is pulled to each channel with a 60.4kΩ precision resistor. Different ground when the voltage on the FB pin is not within ±7.5% output voltages can be programmed with an additional of the internal 0.6V reference. resistor between FB and GND pins. In PolyPhase® opera-
MODE/SYNC (E4):
Burst Mode Select and External Clock tion, connect FB pins for all slave channels to INTVCC and Synchronization of the switching mode regulator. Tie connect VOUT for all paralleled channels together. See the MODE/SYNC to INTV Applications Information section for details. CC for Burst Mode operation with a Rev. A For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photo Design Resources Related Parts
PIN FUNCTIONS VIN (A4, B4, F4, G4):
Power Input Pins connect to the 400mA peak current clamp. Tie MODE/SYNC to GND for drain of the internal top MOSFET for each switching mode pulse-skipping operation, and tie MODE/SYNC to a volt- regulator channel and the internal 5V regulator for the age between 1V and INTVCC – 1.2V for forced continuous control circuitry. Apply input voltages between these mode. Furthermore, connecting this pin to an external pins and GND pins. Recommend placing input decou- clock will synchronize the switch clock to the external pling capacitance directly between each of VIN pins and clock and put the part in forced continuous mode. Do GND pins. not float this pin.
VOUT1 (A1, B1), VOUT2 (A7, B7), VOUT3 (F7, G7), VOUT4 INTVCC (C4):
Internal 5V Regulator Output. The internal
(F1, G1):
Power Output Pins of each switching mode power drivers and control circuits are powered from this regulator channel. Apply output load between these pins voltage. Decouple each pin to GND with a minimum of and GND pins. Recommend placing output decoupling 2.2µF local low ESR ceramic capacitor. INTVCC only starts capacitance directly between these pins and GND pins. up if at least one of the RUN pins is high. See the Applications Information section for paralleling
RUN1 (C3), RUN2 (C5), RUN3 (E5), RUN4 (E3):
Run outputs. Control Input of each switching mode regulator channel.
GND (A2–A3, A5–A6, B2–B3, B5–B6, C2, C6, D3–D5,
Enable regulator operation by tying the specific RUN pin
E2, E6, F2–F3, F5–F6, G2–G3, G5–G6):
Power Ground above 1V. Tying it below 0.35V shuts down the specific Pins for both Input and Output Returns. Use large PCB regulator channel. copper areas to connect all GND together.
FB1 (C1), FB2 (C7), FB3 (E7), FB4 (E1):
The Negative
PGOOD1 (D2), PGOOD2 (D6), PGOOD3 (D7), PGOOD4
Input of the Error Amplifier for each switching mode regu-
(D1):
Output Power Good with Open-Drain Logic of each lator channel. Internally, this pin is connected to VOUT of switching mode regulator channel. PGOOD is pulled to each channel with a 60.4kΩ precision resistor. Different ground when the voltage on the FB pin is not within ±7.5% output voltages can be programmed with an additional of the internal 0.6V reference. resistor between FB and GND pins. In PolyPhase® opera-
MODE/SYNC (E4):
Burst Mode Select and External Clock tion, connect FB pins for all slave channels to INTVCC and Synchronization of the switching mode regulator. Tie connect VOUT for all paralleled channels together. See the MODE/SYNC to INTV Applications Information section for details. CC for Burst Mode operation with a Rev. A For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Typical Applications Package Description Revision History Package Photo Design Resources Related Parts
