Datasheet LTM4622 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Dual Ultrathin 2.5A or Single 5A Step-Down DC/DC μModule Regulator |
| Pages / Page | 28 / 7 — PIN FUNCTIONS. PACKAGE ROW AND COLUMN LABELING MAY VARY. RUN1 (D2), RUN2 … |
| Revision | H |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
PIN FUNCTIONS. PACKAGE ROW AND COLUMN LABELING MAY VARY. RUN1 (D2), RUN2 (B2):. AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
Model Line for this Datasheet
Text Version of Document
link to page 9 link to page 9 LTM4622
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY RUN1 (D2), RUN2 (B2):
Run Control Input of Each
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
Switching Mode Regulator Channel. Enables chip opera-
LAYOUT CAREFULLY.
tion by tying RUN above 1.27V. Tying this pin below 1V
VIN1 (D3, E2), VIN2 (A2, B3):
Power Input Pins. Apply input shuts down the specific regulator channel. Do not float voltage between these pins and GND pins. Recommend this pin. placing input decoupling capacitance directly between
PGOOD1 (D4), PGOOD2 (B4):
Output Power Good with BOTH VIN1 and VIN2 pins and GND pins. Please note Open-Drain Logic of Each Switching Mode Regulator the module internal control circuity is running off VIN1. Channel. PGOOD is pulled to ground when the voltage Channel 2 will not work without a voltage higher that 3.6V on the FB pin is not within ±8% (typical) of the internal present at VIN1. 0.6V reference.
GND (C1 to C2, B5, D5):
Power Ground Pins for Both
TRACK/SS1 (E3), TRACK/SS2 (A3):
Output Tracking and Input and Output Returns. Soft-Start Pin of Each Switching Mode Regulator Channel.
INTVCC (C3):
Internal 3.3V Regulator Output. The internal It allows the user to control the rise time of the output power drivers and control circuits are powered from this voltage. Putting a voltage below 0.6V on this pin bypasses voltage. This pin is internally decoupled to GND with a the internal reference input to the error amplifier, instead 2.2µF low ESR ceramic capacitor. No additional external it servos the FB pin to the TRACK voltage. Above 0.6V, decoupling capacitor needed. the tracking function stops and the internal reference
SYNC/MODE (C5):
Mode Select and External resumes control of the error amplifier. There’s an internal Synchronization Input. Tie this pin to ground to force 1.4µA pull-up current from INTVCC on this pin, so putting continuous synchronous operation at all output loads. a capacitor here provides soft-start function. A default Floating this pin or tying it to INTV internal soft-start ramp forces a minimum soft-start time CC enables high effi- ciency Burst Mode operation at light loads. Drive this of 400µs. pin with a clock to synchronize the LTM4622 switching
FB1 (E4), FB2 (A4):
The Negative Input of the Error frequency. An internal phase-locked loop will force the Amplifier for Each Switching Mode Regulator Channel. bottom power NMOS’s turn on signal to be synchronized Internally, this pin is connected to VOUT with a 60.4k preci- with the rising edge of the clock signal. When this pin is sion resistor. Different output voltages can be programmed driven with a clock, forced continuous mode is automati- with an additional resistor between FB and GND pins. In cally selected. PolyPhase® operation, tying the FB pins together allows
V
for parallel operation. See the Applications Information
OUT1 (D1, E1), VOUT2 (A1, B1):
Power Output Pins of Each Switching Mode Regulator. Apply output load section for details. between these pins and GND pins. Recommend placing
COMP1 (E5), COMP2 (A5):
Current Control Threshold and output decoupling capacitance directly between these Error Amplifier Compensation Point of Each Switching pins and GND pins. Mode Regulator Channel. The current comparator’s trip
FREQ (C4):
Frequency is set internally to 1MHz. An exter- threshold is linearly proportional to this voltage, whose nal resistor can be placed from this pin to GND to increase normal range is from 0.3V to 1.8V. Tie the COMP pins frequency, or from this pin to INTV together for parallel operation. The device is internal com- CC to reduce frequency. See the Applications Information section for frequency pensated. Do not drive this pin. adjustment. Rev. H For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Safety Considerations Layout Checklist/Example Package Description Revision History Package Photo Design Resources Related Parts
PIN FUNCTIONS PACKAGE ROW AND COLUMN LABELING MAY VARY RUN1 (D2), RUN2 (B2):
Run Control Input of Each
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
Switching Mode Regulator Channel. Enables chip opera-
LAYOUT CAREFULLY.
tion by tying RUN above 1.27V. Tying this pin below 1V
VIN1 (D3, E2), VIN2 (A2, B3):
Power Input Pins. Apply input shuts down the specific regulator channel. Do not float voltage between these pins and GND pins. Recommend this pin. placing input decoupling capacitance directly between
PGOOD1 (D4), PGOOD2 (B4):
Output Power Good with BOTH VIN1 and VIN2 pins and GND pins. Please note Open-Drain Logic of Each Switching Mode Regulator the module internal control circuity is running off VIN1. Channel. PGOOD is pulled to ground when the voltage Channel 2 will not work without a voltage higher that 3.6V on the FB pin is not within ±8% (typical) of the internal present at VIN1. 0.6V reference.
GND (C1 to C2, B5, D5):
Power Ground Pins for Both
TRACK/SS1 (E3), TRACK/SS2 (A3):
Output Tracking and Input and Output Returns. Soft-Start Pin of Each Switching Mode Regulator Channel.
INTVCC (C3):
Internal 3.3V Regulator Output. The internal It allows the user to control the rise time of the output power drivers and control circuits are powered from this voltage. Putting a voltage below 0.6V on this pin bypasses voltage. This pin is internally decoupled to GND with a the internal reference input to the error amplifier, instead 2.2µF low ESR ceramic capacitor. No additional external it servos the FB pin to the TRACK voltage. Above 0.6V, decoupling capacitor needed. the tracking function stops and the internal reference
SYNC/MODE (C5):
Mode Select and External resumes control of the error amplifier. There’s an internal Synchronization Input. Tie this pin to ground to force 1.4µA pull-up current from INTVCC on this pin, so putting continuous synchronous operation at all output loads. a capacitor here provides soft-start function. A default Floating this pin or tying it to INTV internal soft-start ramp forces a minimum soft-start time CC enables high effi- ciency Burst Mode operation at light loads. Drive this of 400µs. pin with a clock to synchronize the LTM4622 switching
FB1 (E4), FB2 (A4):
The Negative Input of the Error frequency. An internal phase-locked loop will force the Amplifier for Each Switching Mode Regulator Channel. bottom power NMOS’s turn on signal to be synchronized Internally, this pin is connected to VOUT with a 60.4k preci- with the rising edge of the clock signal. When this pin is sion resistor. Different output voltages can be programmed driven with a clock, forced continuous mode is automati- with an additional resistor between FB and GND pins. In cally selected. PolyPhase® operation, tying the FB pins together allows
V
for parallel operation. See the Applications Information
OUT1 (D1, E1), VOUT2 (A1, B1):
Power Output Pins of Each Switching Mode Regulator. Apply output load section for details. between these pins and GND pins. Recommend placing
COMP1 (E5), COMP2 (A5):
Current Control Threshold and output decoupling capacitance directly between these Error Amplifier Compensation Point of Each Switching pins and GND pins. Mode Regulator Channel. The current comparator’s trip
FREQ (C4):
Frequency is set internally to 1MHz. An exter- threshold is linearly proportional to this voltage, whose nal resistor can be placed from this pin to GND to increase normal range is from 0.3V to 1.8V. Tie the COMP pins frequency, or from this pin to INTV together for parallel operation. The device is internal com- CC to reduce frequency. See the Applications Information section for frequency pensated. Do not drive this pin. adjustment. Rev. H For more information www.analog.com 7 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Decoupling Requirements Operation Applications Information Safety Considerations Layout Checklist/Example Package Description Revision History Package Photo Design Resources Related Parts
