Datasheet ADRV9008-1 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | Integrated Dual RF Receiver |
| Pages / Page | 68 / 1 — Integrated Dual RF Receivers. Data Sheet. ADRV9008-1. FEATURES. Dual … |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
Integrated Dual RF Receivers. Data Sheet. ADRV9008-1. FEATURES. Dual receivers. Maximum receiver bandwidth: 200 MHz
Model Line for this Datasheet
Text Version of Document
Integrated Dual RF Receivers Data Sheet ADRV9008-1 FEATURES
In addition to automatic gain control (AGC), the ADRV9008-1 also
Dual receivers
features flexible external gain control modes, allowing dynamic
Maximum receiver bandwidth: 200 MHz
gain control.
Fully integrated, fractional-N, RF synthesizers
The received signals are digitized with a set of four, high dynamic
Fully integrated clock synthesizer
range, continuous time, sigma-delta (Σ-Δ) ADCs that provide
Multichip phase synchronization for RF LO and baseband clocks
inherent antialiasing. The combination of the direct conversion
JESD204B datapath interface
architecture (which does not suffer from out of band image
Tuning range (center frequency): 75 MHz to 6000 MHz
mixing) and the lack of aliasing reduces the requirements of the RF
APPLICATIONS
filters compared to the requirements of traditional intermediate frequency (IF) receivers.
3G/4G/5G FDD, macrocell base stations Wideband active antenna systems
The fully integrated phase-locked loop (PLL) provides high
Massive multiple input, multiple output (MIMO)
performance, low power, fractional-N, RF synthesis for the
Phased array radar
receiver signal paths. An additional synthesizer generates the
Electronic warfare
clocks needed for the converters, digital circuits, and serial
Military communications
interface. A multichip synchronization mechanism synchronizes
Portable test equipment
the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. The ADRV9008-1 features
GENERAL DESCRIPTION
the isolation that high performance base station applications The ADRV9008-1 is a highly integrated, dual radio frequency (RF), require. All voltage controlled oscillators (VCOs) and loop agile receiver offering integrated synthesizers and digital signal filter components are integrated. processing functions. The IC delivers a versatile combination of The high speed JESD204B interface supports up to 12.288 Gbps high performance and low power consumption required by lane rates, resulting in a single lane per receiver in the widest 3G/4G/5G macrocel , frequency division duplex (FDD), base bandwidth mode. The interface also supports interleaved mode station applications. for lower bandwidths, reducing the total number of high speed The receive path consists of two independent, wide bandwidth, data interface lanes to one. Both fixed and floating point data direct conversion receivers with state-of-the-art dynamic range. formats are supported. The floating point format allows internal The complete receive subsystem includes automatic and manual AGC to be invisible to the demodulator device. attenuation control, dc offset correction, quadrature error The core of the ADRV9008-1 can be powered directly from correction (QEC), and digital filtering, eliminating the need for 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire these functions in the digital baseband. RF front-end control and serial port. Comprehensive power-down modes are included to several auxiliary functions, such as analog-to-digital converters minimize power consumption during normal use. The (ADCs), digital-to-analog converters (DACs), and general-purpose ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-bal chip input/outputs (GPIOs) for the power amplifier (PA), are also scale ball grid array (CSP_BGA). integrated.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
In addition to automatic gain control (AGC), the ADRV9008-1 also
Dual receivers
features flexible external gain control modes, allowing dynamic
Maximum receiver bandwidth: 200 MHz
gain control.
Fully integrated, fractional-N, RF synthesizers
The received signals are digitized with a set of four, high dynamic
Fully integrated clock synthesizer
range, continuous time, sigma-delta (Σ-Δ) ADCs that provide
Multichip phase synchronization for RF LO and baseband clocks
inherent antialiasing. The combination of the direct conversion
JESD204B datapath interface
architecture (which does not suffer from out of band image
Tuning range (center frequency): 75 MHz to 6000 MHz
mixing) and the lack of aliasing reduces the requirements of the RF
APPLICATIONS
filters compared to the requirements of traditional intermediate frequency (IF) receivers.
3G/4G/5G FDD, macrocell base stations Wideband active antenna systems
The fully integrated phase-locked loop (PLL) provides high
Massive multiple input, multiple output (MIMO)
performance, low power, fractional-N, RF synthesis for the
Phased array radar
receiver signal paths. An additional synthesizer generates the
Electronic warfare
clocks needed for the converters, digital circuits, and serial
Military communications
interface. A multichip synchronization mechanism synchronizes
Portable test equipment
the phase of the RF local oscillator (LO) and baseband clocks between multiple ADRV9008-1 chips. The ADRV9008-1 features
GENERAL DESCRIPTION
the isolation that high performance base station applications The ADRV9008-1 is a highly integrated, dual radio frequency (RF), require. All voltage controlled oscillators (VCOs) and loop agile receiver offering integrated synthesizers and digital signal filter components are integrated. processing functions. The IC delivers a versatile combination of The high speed JESD204B interface supports up to 12.288 Gbps high performance and low power consumption required by lane rates, resulting in a single lane per receiver in the widest 3G/4G/5G macrocel , frequency division duplex (FDD), base bandwidth mode. The interface also supports interleaved mode station applications. for lower bandwidths, reducing the total number of high speed The receive path consists of two independent, wide bandwidth, data interface lanes to one. Both fixed and floating point data direct conversion receivers with state-of-the-art dynamic range. formats are supported. The floating point format allows internal The complete receive subsystem includes automatic and manual AGC to be invisible to the demodulator device. attenuation control, dc offset correction, quadrature error The core of the ADRV9008-1 can be powered directly from correction (QEC), and digital filtering, eliminating the need for 1.3 V and 1.8 V regulators and is controlled via a standard 4-wire these functions in the digital baseband. RF front-end control and serial port. Comprehensive power-down modes are included to several auxiliary functions, such as analog-to-digital converters minimize power consumption during normal use. The (ADCs), digital-to-analog converters (DACs), and general-purpose ADRV9008-1 is packaged in a 12 mm × 12 mm, 196-bal chip input/outputs (GPIOs) for the power amplifier (PA), are also scale ball grid array (CSP_BGA). integrated.
Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
