Datasheet ADRV9008-1 (Analog Devices) - 3
| Manufacturer | Analog Devices |
| Description | Integrated Dual RF Receiver |
| Pages / Page | 68 / 3 — Data Sheet. ADRV9008-1. FUNCTIONAL BLOCK DIAGRAM. Rx2. RX1_IN+. Rx1. … |
| File Format / Size | PDF / 1.9 Mb |
| Document Language | English |
Data Sheet. ADRV9008-1. FUNCTIONAL BLOCK DIAGRAM. Rx2. RX1_IN+. Rx1. SYNCIN0± SYNCIN1±. RX1_IN–. ADC. RX2_IN+. SERDOUT0± SERDOUT1±. LPF
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Text Version of Document
Data Sheet ADRV9008-1 FUNCTIONAL BLOCK DIAGRAM Rx2 ADRV9008-1 RX1_IN+ Rx1 SYNCIN0± SYNCIN1± RX1_IN– ADC RX2_IN+ SERDOUT0± SERDOUT1± LPF RX2_IN– SERDOUT2± DIGITAL SERDOUT3± PROCESSING SYSREF_IN± DECIMATION ADC GP_INTERRUPT pFIR AGC RX1_ENABLE LPF DC OFFSET RX2_ENABLE QEC JESD204B RESET RF_EXT_LO_I/O+ CIF/RIF TEST RF LO Arm SYNTHESIZER Cortex-M3 SCLK RF_EXT_LO_I/O– CS SDO SDIO GPIOs, AUXILIARY ADCs, CLOCK REF_CLK_IN + AND AUXILIARY DACs GENERATION REF_CLK_IN –
001
GPIO_3p3_x GPIO_x AUXADC_x
16830- Figure 1. Rev. 0 | Page 3 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
001
GPIO_3p3_x GPIO_x AUXADC_x
16830- Figure 1. Rev. 0 | Page 3 of 68 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Current and Power Consumption Specifications Timing Diagrams Absolute Maximum Ratings Reflow Profile Thermal Management Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics 75 MHz to 525 MHz Band 650 MHz to 3000 MHz Band 3400 MHz to 4800 MHz Band 5100 MHz to 5900 MHz Band Receiver Input Impedance Terminology Theory of Operation Receivers Clock Input Synthesizers RF PLL Clock PLL SPI JTAG Boundary Scan Power Supply Sequence GPIO_x Pins Auxiliary Converters AUXADC_x Auxiliary DAC x JESD204B Data Interface Applications Information PCB Layout and Power Supply Recommendations Overview PCB Material and Stackup Selection Fanout and Trace Space Guidelines Component Placement and Routing Guidelines Signals with Highest Routing Priority Signals with Second Routing Priority Signals with Lowest Routing Priority RF and JESD204B Transmission Line Layout RF Routing Guidelines JESD204B Trace Routing Recommendations Routing Recommendations Stripline Transmission Lines vs. Microstrip Transmission Lines Isolation Techniques Used on the ADRV9008-1W/PCBZ Isolation Goals Isolation Between JESD204B Lines RF Port Interface Information RF Port Impedance Data Advanced Design System (ADS) Setup Using the DataAccessComponent and SEDZ File General Receiver Path Interface Impedance Matching Network Examples Outline Dimensions Ordering Guide
