Datasheet AD9361 (Analog Devices)
| Manufacturer | Analog Devices |
| Description | RF Agile Transceiver |
| Pages / Page | 36 / 1 — RF Agile Transceiver. Data Sheet. AD9361. FEATURES. FUNCTIONAL BLOCK … |
| Revision | F |
| File Format / Size | PDF / 648 Kb |
| Document Language | English |
RF Agile Transceiver. Data Sheet. AD9361. FEATURES. FUNCTIONAL BLOCK DIAGRAM
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RF Agile Transceiver Data Sheet AD9361 FEATURES FUNCTIONAL BLOCK DIAGRAM RF 2 × 2 transceiver with integrated 12-bit DACs and ADCs RX1B_P, RX1B_N AD9361 TX band: 47 MHz to 6.0 GHz RX1A_P, ADC RX band: 70 MHz to 6.0 GHz RX1A_N RX1C_P, Supports TDD and FDD operation RX1C_N Tunable channel bandwidth: <200 kHz to 56 MHz RX2B_P, RX2B_N Dual receivers: 6 differential or 12 single-ended inputs RX2A_P, ADC E Superior receiver sensitivity with a noise figure of 2 dB at RX2A_N C A RX2C_P, F P0_[D11:D0]/ 800 MHz LO R RX2C_N RX LO TX_[D5:D0] TE RX gain control TX_MON1 IN P1_[D11:D0]/ TX LO RX_[D5:D0] Real-time monitor and control signals for manual gain TA TX1A_P, A DAC D TX1A_N Independent automatic gain control TX1B_P, Dual transmitters: 4 differential outputs TX1B_N Highly linear broadband transmitter TX_MON2 TX EVM: ≤−40 dB TX2A_P, DAC TX2A_N TX noise: ≤−157 dBm/Hz noise floor TX2B_P, RADIO C C C TX monitor: ≥66 dB dynamic range with 1 dB accuracy TX2B_N GPO SWITCHING AD DA DA Integrated fractional-N synthesizers SPI CTRL PLLs CLK_OUT 2.4 Hz maximum local oscillator (LO) step size CTRL Multichip synchronization AUXADC AUXDACx XTALP XTALN CMOS/LVDS digital interface NOTES
01
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],
-0 453
APPLICATIONS AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
10 Figure 1.
Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems GENERAL DESCRIPTION
impulse response (FIR) filters to produce a 12-bit output signal at The AD9361 is a high performance, highly integrated radio the appropriate sample rate. frequency (RF) Agile Transceiver™ designed for use in 3G and The transmitters use a direct conversion architecture that achieves 4G base station applications. Its programmability and wideband high modulation accuracy with ultralow noise. This transmitter capability make it ideal for a broad range of transceiver applications. design produces a best in class TX error vector magnitude (EVM) The device combines a RF front end with a flexible mixed-signal of <−40 dB, allowing significant system margin for the external baseband section and integrated frequency synthesizers, simplifying power amplifier (PA) selection. The on-board transmit (TX) design-in by providing a configurable digital interface to a power monitor can be used as a power detector, enabling highly processor. The AD9361 receiver LO operates from 70 MHz to accurate TX power measurements. 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz The fully integrated phase-locked loops (PLLs) provide low range, covering most licensed and unlicensed bands. Channel power fractional-N frequency synthesis for all receive and bandwidths from less than 200 kHz to 56 MHz are supported. transmit channels. Channel isolation, demanded by frequency The two independent direct conversion receivers have state-of-the- division duplex (FDD) systems, is integrated into the design. art noise figure and linearity. Each receive (RX) subsystem includes All VCO and loop filter components are integrated. independent automatic gain control (AGC), dc offset correction, The core of the AD9361 can be powered directly from a 1.3 V quadrature correction, and digital filtering, thereby eliminating regulator. The IC is controlled via a standard 4-wire serial port the need for these functions in the digital baseband. The AD9361 and four real-time input/output control pins. Comprehensive also has flexible manual gain modes that can be externally power-down modes are included to minimize power consumption controlled. Two high dynamic range analog-to-digital converters during normal use. The AD9361 is packaged in a 10 mm × 10 mm, (ADCs) per channel digitize the received I and Q signals and pass 144-ball chip scale package ball grid array (CSP_BGA). them through configurable decimation filters and 128-tap finite
Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
01
1. SPI, CTRL, P0_[D11:D0]/TX_[D5:D0], P1_[D11:D0]/RX_[D5:D0],
-0 453
APPLICATIONS AND RADIO SWITCHING CONTAIN MULTIPLE PINS.
10 Figure 1.
Point to point communication systems Femtocell/picocell/microcell base stations General-purpose radio systems GENERAL DESCRIPTION
impulse response (FIR) filters to produce a 12-bit output signal at The AD9361 is a high performance, highly integrated radio the appropriate sample rate. frequency (RF) Agile Transceiver™ designed for use in 3G and The transmitters use a direct conversion architecture that achieves 4G base station applications. Its programmability and wideband high modulation accuracy with ultralow noise. This transmitter capability make it ideal for a broad range of transceiver applications. design produces a best in class TX error vector magnitude (EVM) The device combines a RF front end with a flexible mixed-signal of <−40 dB, allowing significant system margin for the external baseband section and integrated frequency synthesizers, simplifying power amplifier (PA) selection. The on-board transmit (TX) design-in by providing a configurable digital interface to a power monitor can be used as a power detector, enabling highly processor. The AD9361 receiver LO operates from 70 MHz to accurate TX power measurements. 6.0 GHz and the transmitter LO operates from 47 MHz to 6.0 GHz The fully integrated phase-locked loops (PLLs) provide low range, covering most licensed and unlicensed bands. Channel power fractional-N frequency synthesis for all receive and bandwidths from less than 200 kHz to 56 MHz are supported. transmit channels. Channel isolation, demanded by frequency The two independent direct conversion receivers have state-of-the- division duplex (FDD) systems, is integrated into the design. art noise figure and linearity. Each receive (RX) subsystem includes All VCO and loop filter components are integrated. independent automatic gain control (AGC), dc offset correction, The core of the AD9361 can be powered directly from a 1.3 V quadrature correction, and digital filtering, thereby eliminating regulator. The IC is controlled via a standard 4-wire serial port the need for these functions in the digital baseband. The AD9361 and four real-time input/output control pins. Comprehensive also has flexible manual gain modes that can be externally power-down modes are included to minimize power consumption controlled. Two high dynamic range analog-to-digital converters during normal use. The AD9361 is packaged in a 10 mm × 10 mm, (ADCs) per channel digitize the received I and Q signals and pass 144-ball chip scale package ball grid array (CSP_BGA). them through configurable decimation filters and 128-tap finite
Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2013–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS CURRENT CONSUMPTION—VDD_INTERFACE CURRENT CONSUMPTION—VDDD1P3_DIG AND VDDAx (COMBINATION OF ALL 1.3 V SUPPLIES) ABSOLUTE MAXIMUM RATINGS REFLOW PROFILE THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS 800 MHz FREQUENCY BAND 2.4 GHz FREQUENCY BAND 5.5 GHz FREQUENCY BAND THEORY OF OPERATION GENERAL RECEIVER TRANSMITTER CLOCK INPUT OPTIONS SYNTHESIZERS RF PLLs BB PLL DIGITAL DATA INTERFACE DATA_CLK Signal FB_CLK Signal RX_FRAME Signal ENABLE STATE MACHINE SPI Control Mode Pin Control Mode SPI INTERFACE CONTROL PINS Control Outputs (CTRL_OUT[7:0]) Control Inputs (CTRL_IN[3:0]) GPO PINS (GPO_3 TO GPO_0) AUXILIARY CONVERTERS AUXADC AUXDAC1 and AUXDAC2 POWERING THE AD9361 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
