Datasheet ADN8833 (Analog Devices) - 4

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ADN8833 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ Max Unit
Leakage Current P-MOSFET ISW_P_LKG 0.1 10 µA N-MOSFET ISW_N_LKG 0.1 10 µA SW Node Rise Time1 tSW_R CSW = 1 nF 1 ns PWM Duty Cycle2 DSW 6 93 % SFB Input Bias Current ISFB 1 2 µA PWM OSCILLATOR Internal Oscil ator Frequency fOSC EN/SY high 1.85 2.0 2.15 MHz EN/SY Input Voltage Low VEN/SY_ILOW 0.8 V High VEN/SY_IHIGH 2.1 V External Synchronization Frequency fSYNC 1.85 3.25 MHz Synchronization Pulse Duty Cycle DSYNC 10 90 % EN/SY Rising to PWM Rising Delay tSYNC_PWM 50 ns EN/SY to PWM Lock Time tSY_LOCK Number of SYNC cycles 10 Cycles EN/SY Input Current IEN/SY 0.3 0.5 µA Pul -Down Current 0.3 0.5 µA DRIVER CONTROL INPUT Input Voltage Range VCONT 0 VVREF V Input Resistance RCONT 40 kΩ Input Capacitance1 CCONT 40 pF TEC CURRENT LIMIT ILIM Input Voltage Range Cooling VILIMC 1.3 VVREF − 0.2 V Heating VILIMH 0.2 1.2 V Current-Limit Threshold Cooling VILIMC_TH VITEC = 0.5 V 1.98 2.0 2.02 V Heating VILIMH_TH VITEC = 2 V 0.48 0.5 0.52 V ILIM Input Current Heating IILIMH −0.2 +0.2 µA Cooling IILIMC Sourcing current 37.5 40 42.5 µA Cooling to Heating Current Detection ICOOL_HEAT_TH 40 mA Threshold TEC VOLTAGE LIMIT Voltage Limit Gain AVLIM (VLDR − VSFB)/VVLIM 2 V/V VLIM/SD Input Voltage Range1 VVLIM 0.2 VVDD/2 V VLIM/SD Input Current Cooling IILIMC VOUT2 < VVREF/2 −0.2 +0.2 µA Heating IILIMH VOUT2 > VVREF/2, sinking current 8 10 12.2 µA TEC CURRENT MEASUREMENT (WLCSP) Current Sense Gain RCS VPVIN = 3.3 V 0.525 V/A VPVIN = 5 V 0.535 V/A Current Measurement Accuracy ILDR_ERROR 700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V −10 +10 % 800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V −10 +10 % ITEC Voltage Accuracy VITEC_@_700_mA VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS 1.455 1.618 1.779 V VITEC_@_−700_mA VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS 0.794 0.883 0.971 V VITEC_@_800_mA VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS 1.510 1.678 1.846 V VITEC_@_−800_mA VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS 0.739 0.822 0.905 V Rev. B | Page 4 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE