Datasheet ADN8833 (Analog Devices) - 5

Data Sheet ADN8833 Parameter Symbol Test Conditions/Comments Min Typ Max Unit
TEC CURRENT MEASUREMENT (LFCSP) Current Sense Gain RCS VPVIN = 3.3 V 0.525 V/A VPVIN = 5 V 0.525 V/A Current Measurement Accuracy ILDR_ERROR 700 mA ≤ ILDR ≤ 1 A, VPVIN = 3.3 V −15 +15 % 800 mA ≤ ILDR ≤ 1 A, VPVIN = 5 V −15 +15 % ITEC Voltage Accuracy VITEC_@_700_mA VPVIN = 3.3 V, cooling, VVREF/2 + ILDR × RCS 1.374 1.618 1.861 V VITEC_@_−700_mA VPVIN = 3.3 V, heating, VVREF/2 − ILDR × RCS 0.750 0.883 1.015 V VITEC_@_800_mA VPVIN = 5 V, cooling, VVREF/2 + ILDR × RCS 1.419 1.678 1.921 V VITEC_@_−800_mA VPVIN = 5 V, heating, VVREF/2 − ILDR × RCS 0.705 0.830 0.955 V ITEC Voltage Output Range VITEC ITEC = 0 A 0 VVREF − 0.05 V ITEC Bias Voltage VITEC ILDR = 0 A 1.225 1.250 1.285 V Maximum ITEC Output Current IITEC −2 +2 mA TEC VOLTAGE MEASUREMENT Voltage Sense Gain AVTEC 0.24 0.25 0.26 V/V Voltage Measurement Accuracy VVTEC_@_1_V VLDR − VSFB = 1 V, VVREF/2 + AVTEC × 1.475 1.50 1.525 V (VLDR − VSFB) VTEC Output Voltage Range VVTEC 0.005 2.625 V VTEC Bias Voltage VVTEC_B VLDR = VSFB 1.225 1.250 1.285 V Maximum VTEC Output Current RVTEC −2 +2 mA INTERNAL SOFT START Soft Start Time tSS 150 ms VLIM/SD SHUTDOWN VLIM/SD Low Voltage Threshold VVLIM/SD_THL 0.07 V THERMAL SHUTDOWN Thermal Shutdown Threshold TSHDN_TH 170 °C Thermal Shutdown Hysteresis TSHDN_HYS 17 °C 1 This specification is guaranteed by design. 2 This specification is guaranteed by characterization. Rev. B | Page 5 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS DETAILED FUNCTIONAL BLOCK DIAGRAM THEORY OF OPERATION DIGITAL PID CONTROL POWERING THE DRIVER ENABLE AND SHUTDOWN OSCILLATOR CLOCK FREQUENCY External Clock Operation Connecting Multiple ADN8833 Devices SOFT START ON POWER-UP TEC VOLTAGE/CURRENT MONITOR Voltage Monitor Current Monitor MAXIMUM TEC VOLTAGE LIMIT Using a Resistor Divider to Set the TEC Voltage Limit MAXIMUM TEC CURRENT LIMIT Using a Resistor Divider to Set the TEC Current Limit APPLICATIONS INFORMATION TYPICAL APPLICATION WITH DIGITAL PID USING A DAC THERMISTOR SETUP MOSFET DRIVER AMPLIFIERS PWM OUTPUT FILTER REQUIREMENTS Inductor Selection Capacitor Selection INPUT CAPACITOR SELECTION POWER DISSIPATION PWM Regulator Power Dissipation Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Linear Regulator Power Dissipation PCB LAYOUT GUIDELINES BLOCK DIAGRAMS AND SIGNAL FLOW GUIDELINES FOR REDUCING NOISE AND MINIMIZING POWER LOSS General PCB Layout Guidelines PWM Power Stage Layout Guidelines Linear Power Stage Layout Guidelines EXAMPLE PCB LAYOUT USING TWO LAYERS OUTLINE DIMENSIONS ORDERING GUIDE