Datasheet ADCMP563, ADCMP564 (Analog Devices)

Dual, High Speed ECL Comparators Data Sheet ADCMP563/ ADCMP564 FEATURES FUNCTIONAL BLOCK DIAGRAMS Differential ECL-compatible outputs HYS* 700 ps propagation delay input to output NONINVERTING 75 ps propagation delay dispersion Q OUTPUT INPUT Input common-mode range: –2.0 V to +3.0 V ADCMP563/ Robust input protection ADCMP564 INVERTING Differential latch control Q OUTPUT INPUT Internal latch pull-up resistors Power supply rejection greater than 85 dB LATCH ENABLE LATCH ENABLE 700 ps minimum pulse width INPUT INPUT 1.5 GHz equivalent input rise time bandwidth *ADCMP564 ONLY
04650-0-001 Figure 1.
Typical output rise/fall time of 500 ps ESD protection > 4kV HBM, >200V MM QA 1 16 QB Programmable hysteresis QA 2 15 QB APPLICATIONS GND 3 14 GND Automatic test equipment ADCMP563 LEA 4 13 LEB BRQ High speed instrumentation LEA 5 TOP VIEW 12 LEB (Not to Scale) Scope and logic analyzer front ends V 6 11 V EE CC Window comparators –INA 7 10 –INB High speed line receivers +INA 8 9 +INB Threshold detection
04650-0-002
Peak detection
Figure 2. ADCMP563 16-Lead QSOP
High speed triggers Patient diagnostics GND 1 20 GND Hand-held test instruments QA 2 19 QB Zero crossing detectors QA 3 18 QB Line receivers and signal restoration GND 4 ADCMP564 17 GND BRQ Clock drivers LEA 5 16 LEB TOP VIEW GENERAL DESCRIPTION (Not to Scale) LEA 6 15 LEB V 7 14 V
The ADCMP563/ADCMP564 are high speed comparators
EE CC –INA 8 13 –INB
fabricated on Analog Devices’ proprietary XFCB process. The
+INA 9 12 +INB
devices feature a 700 ps propagation delay with less than 75 ps
HYSA 10 11 HYSB
overdrive dispersion. Dispersion, a measure of the difference in 04650-0-012 propagation delay under differing overdrive conditions, is a partic- Figure 3. ADCMP564 20-Lead QSOP
A A EE
ularly important characteristic of high speed comparators. A separate
V ND LE LE G
programmable hysteresis pin is available on the ADCMP564.
16 15 14 13
A differential input stage permits consistent propagation delay
–INA 1 12 QA
with a wide variety of signals in the common-mode range from
+INA 2 11 QA ADCMP563
−2.0 V to +3.0 V. Outputs are complementary digital signals that
+INB 3 BCP 10 QB TOP VIEW
are ful y compatible with ECL 10 K and 10 KH logic families.
–INB 4 9 QB (Not to Scale)
The outputs provide sufficient drive current to directly drive
5 6 7 8
transmission lines terminated in 50 Ω to −2 V. A latch input,
CC EB EB ND
which is included, permits tracking, track-and-hold, or sample-
V L L G
026 0- and-hold modes of operation. The latch input pins contain internal
NOTES 1. THE EXPOSED PAD SHOULD BE EITHER CONNECTED TO VEE OR LEFT FLOATING.
04650- pull-ups that set the latch in tracking mode when left open. Figure 4. ADCMP563 16-Lead LFCSP The ADCMP563/ADCMP564 are specified over the industrial temperature range (−40°C to +85°C).
Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAMS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TIMING INFORMATION APPLICATION INFORMATION CLOCK TIMING RECOVERY OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATION DELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENT TYPICAL APPLICATION CIRCUITS OUTLINE DIMENSIONS ORDERING GUIDE