Datasheet ADCMP572, ADCMP573 (Analog Devices) - 6

link to page 7
ADCMP572/ADCMP573 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS I D S D CCV GN HY GN 61 5 3 1 41 1 V 1 12 TP VCCO V 2 ADCMP572 11 P Q ADCMP573 V 3 10 Q N TOP VIEW V 4 9 TN VCCO 5 6 7 8 I CC LE LE TT V /V O CCV NOTES
26 0
1. LEAVE EPAD FLOATING UNLESS IMPROVED THERMAL OR MECHANICAL
9-
STABILITY IS DESIRED, IN WHICH CASE SOLDER IT TO THE APPLICATION BOARD.
4400 Figure 2. ADCMP572/ADCMP573 Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1 VTP Termination Resistor Return Pin for VP Input. 2 VP Noninverting Analog Input. 3 VN Inverting Analog Input. 4 VTN Termination Resistor Return Pin for VN Input. 5, 16 VCCI Positive Supply Voltage for Input Stage. 6 LE Latch Enable Input Pin, Inverting Side. In compare mode (LE = low), the output tracks changes at the input of the comparator. In latch mode (LE = high), the output reflects the input state just prior to the comparator’s being placed into latch mode. LE must be driven in complement with LE. 7 LE Latch Enable Input Pin, Noninverting Side. In compare mode (LE = high), the output tracks changes at the input of the comparator. In latch mode (LE = low), the output reflects the input state just prior to the comparator’s being placed into latch mode. LE must be driven in complement with LE. 8 VCCO/VTT Termination Return Pin for the LE/LE Input Pins. For the ADCMP572 (CML output stage), this pin is internally connected to and also should be externally connected to the positive VCCO supply. For the ADCMP573 (RSPECL output stage), this pin should normally be connected to the VCCO – 2 V termination potential. 9, 12 VCCO Positive Supply Voltage for the CML/RSPECL Output Stage. 13, 15 GND Ground. 10 Q Inverting Output. Q is at logic low if the analog voltage at the noninverting input, VP, is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6 and 7) for more information. 11 Q Noninverting Output. Q is at logic high if the analog voltage at the noninverting input VP is greater than the analog voltage at the inverting input, VN, provided the comparator is in compare mode. See the LE/LE descriptions (Pins 6 and 7) for more information. 14 HYS Hysteresis Control Pin. Leave this pin disconnected for zero hysteresis. Connect to GND with a suitably sized resistor to add the desired amount of hysteresis. Refer to Figure 7 for proper sizing of RHYS hysteresis control resistor. Isolated The metallic back surface of the package is not electrically connected to any part of the circuit, and it can be left Heat Sink floating for best electrical isolation between the package handle and the substrate of the die. However, it can be soldered to the application board if improved thermal and/or mechanical stability is desired. Exposed metal at package corners is connected to the heat sink paddle. EPAD Exposed Pad. Leave EPAD floating unless improved thermal or mechanical stability is desired, in which case solder it to the application board. Rev. B | Page 6 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML/RSPECL OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATIONDELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENTS TYPICAL APPLICATION CIRCUITS TIMING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE