Datasheet ADCMP572, ADCMP573 (Analog Devices) - 9

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Data Sheet ADCMP572/ADCMP573 APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING
prevent output ringing and pulse width dependent propagation The ADCMP572/ADCMP573 comparators are very high speed delay dispersion. For the most timing critical applications where SiGe devices. Consequently, it is essential to use proper high speed transmission line reflections pose the greatest risk to performance, design techniques to achieve the specified performance. Of critical the ADCMP572 provides the best match to 50 Ω output importance is the use of low impedance supply planes, particularly transmission paths. the output supply plane (V
VCCO
CCO) and the ground plane (GND). Individual supply planes are recommended as part of a multilayer board. Providing the lowest inductance return path for switching
50
currents ensures the best possible performance in the target application.
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It is important to adequately bypass the input and output supplies.
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A 1 μF electrolytic bypass capacitor should be placed within several inches of each power supply pin to ground. In addition, multiple high quality 0.01 μF bypass capacitors should be placed as close as possible to each of the V
16mA
CCI and VCCO supply pins and should be connected to the GND plane with redundant vias. High frequency bypass capacitors should be carefully selected for
GND
04409-037 minimum inductance and ESR. Parasitic layout inductance should Figure 15. Simplified Schematic Diagram of be avoided to maximize the effectiveness of the bypass at high the ADCMP572 CML Output Stage frequencies.
V
If the input and output supplies are connected separately such
CCO
that VCCI ≠ VCCO, care should be taken to bypass each of these supplies separately to the GND plane. A bypass capacitor should not be connected between them. It is recommended that the GND plane separate the VCCI and VCCO planes when the circuit board layout is designed to minimize coupling between the two supplies and to take advantage of the additional bypass capaci-
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tance from each respective supply to the ground plane. This
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enhances the performance when split input/output supplies are used. If the input and output supplies are connected together for single-supply operation such that VCCI = VCCO, coupling between the two supplies is unavoidable; however, every effort should be
GND
04409-038 made to keep the supply plane adjacent to the GND plane to Figure 16. Simplified Schematic Diagram of maximize the additional bypass capacitance this arrangement the ADCMP573 RSPECL Output Stage provides.
USING/DISABLING THE LATCH FEATURE CML/RSPECL OUTPUT STAGE
The latch inputs (LE/LE) are active low for latch mode and are Specified propagation delay dispersion performance can be internally terminated with 50 Ω resistors to Pin 8. This pin achieved only by using proper transmission line terminations. corresponds to and is internally connected to the VCCO supply The outputs of the ADCMP572 are designed to directly drive for the CML-compatible ADCMP572. With the aid of these 400 mV into 50 Ω cable, microstrip, or strip line transmission resistors, the ADCMP572 latch function can be disabled by lines properly terminated to the VCCO supply plane. The CML connecting the LE pin to GND with an external pull-down output stage is shown in the simplified schematic diagram of resistor and leaving the LE pin unconnected. To avoid excessive Figure 15. The outputs are each back terminated with 50 Ω for power dissipation, the resistor should be 750 Ω when VCCO = best transmission line matching. The RSPECL outputs of the 3.3 V, and 1.2 kΩ when VCCO = 5.2 V. In the PECL-compatible ADCMP573 are illustrated in Figure 16 and should be terminated ADCMP573, the VTT pin should be connected externally to the to VCCO − 2 V. As an alternative, Thevenin equivalent termination PECL termination supply at VCCO – 2 V. The latch can then be networks can be used in either case if the direct termination disabled by connecting the LE pin to VCCO with an external voltage is not readily available. If high speed output signals must 500 Ω resistor and leaving the LE pin disconnected. In this case, be routed more than a centimeter, microstrip or strip line the resistor value does not depend on the VCCO supply voltage. techniques are essential to ensure proper transition times and to Rev. B | Page 9 of 14 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL CHARACTERISTICS ABSOLUTE MAXIMUM RATINGS THERMAL CONSIDERATIONS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATIONS INFORMATION POWER/GROUND LAYOUT AND BYPASSING CML/RSPECL OUTPUT STAGE USING/DISABLING THE LATCH FEATURE OPTIMIZING HIGH SPEED PERFORMANCE COMPARATOR PROPAGATIONDELAY DISPERSION COMPARATOR HYSTERESIS MINIMUM INPUT SLEW RATE REQUIREMENTS TYPICAL APPLICATION CIRCUITS TIMING INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE