Datasheet ADP322, ADP323 (Analog Devices) - 5

Data Sheet ADP322/ADP323 ABSOLUTE MAXIMUM RATINGS Table 3.
Junction to ambient thermal resistance (θJA) of the package is
Parameter Rating
based on modeling and calculation using a 4-layer board. The junction to ambient thermal resistance is highly dependent on VIN1/VIN2, VIN3, VBIAS to GND −0.3 V to +6.5 V the application and board layout. In applications where high VOUT1, VOUT2, FB1, FB2 to GND −0.3 V to VIN1/VIN2 maximum power dissipation exists, close attention to thermal VOUT3, FB3 to GND −0.3 V to VIN3 board design is required. The value of θ EN1, EN2, EN3 to GND −0.3 V to +6.5 V JA can vary, depending on PCB material, layout, and environmental conditions. The Storage Temperature Range −65°C to +150°C specified values of θ Operating Junction Temperature Range −40°C to +125°C JA are based on a 4-layer, 4 inch × 3 inch circuit board. See JEDEC JESD 51-9 for detailed information on the Soldering Conditions JEDEC J-STD-020 board construction. For additional information, see the AN-617 Stresses at or above those listed under Absolute Maximum Application Note, MicroCSP™ Wafer Level Chip Scale Package. Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these ΨJB is the junction to board thermal characterization parameter or any other conditions above those indicated in the operational with units of °C/W. ΨJB of the package is based on modeling and section of this specification is not implied. Operation beyond calculation using a 4-layer board. The JESD51-12, Guidelines for the maximum operating conditions for extended periods may Reporting and Using Package Thermal Information, states that affect product reliability. thermal characterization parameters are not the same as thermal resistances. ΨJB measures the component power flowing through
THERMAL DATA
multiple thermal paths rather than a single path as in thermal Absolute maximum ratings apply individually only, not in resistance, θJB. Therefore, ΨJB thermal paths include convection combination. from the top of the package as wel as radiation from the package, factors that make Ψ The ADP322/ADP323 triple LDO can be damaged when the JB more useful in real-world applications. Maximum junction temperature (T junction temperature limits are exceeded. Monitoring ambient J) is calculated from the board temperature (T temperature does not guarantee that the junction temperature B) and power dissipation (PD) using the following formula: (TJ) is within the specified temperature limits. In applications with high power dissipation and poor thermal resistance, the TJ = TB + (PD × ΨJB) maximum ambient temperature may have to be derated. In See JEDEC JESD51-8 and JESD51-12 for more detailed infor- applications with moderate power dissipation and low printed mation about ΨJB. circuit board (PCB) thermal resistance, the maximum ambient
THERMAL RESISTANCE
temperature can exceed the maximum limit as long as the junction temperature is within specification limits. θJA and ΨJB are specified for the worst case conditions, that is, a The junction temperature (T device soldered in a circuit board for surface-mount packages. J) of the device is dependent on the ambient temperature (TA), the power dissipation of the device
Table 4.
(PD), and the junction to ambient thermal resistance of the package
Package Type θJA ΨJB Unit
(θJA). Maximum junction temperature (TJ) is calculated from 16-Lead, 3 mm × 3 mm LFCSP 49.5 25.2 °C/W the ambient temperature (TA) and power dissipation (PD) using the following formula:
ESD CAUTION
TJ = TA + (PD × θJA) Rev. E | Page 5 of 24 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR, RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT ENABLE FEATURE NOISE REDUCTION OF THE ADP323 IN ADJUSTABLE MODE CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE NOTES