Datasheet AD707 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Ultralow Drift Op Amp |
| Pages / Page | 8 / 7 — AD707. 18-BIT SETTLING TIME. 140 dB CMRR INSTRUMENTATION AMPLIFIER. … |
| File Format / Size | PDF / 298 Kb |
| Document Language | English |
AD707. 18-BIT SETTLING TIME. 140 dB CMRR INSTRUMENTATION AMPLIFIER. 20,000. CIRCUIT GAIN = –––––– + 1. –IN. 10k. REFERENCE. OBSOLETE
Model Line for this Datasheet
Text Version of Document
AD707 18-BIT SETTLING TIME 140 dB CMRR INSTRUMENTATION AMPLIFIER
Figure 22 shows the AD707 settling to within 80 µV of its final The extremely tight dc specifications of the AD707 enable the value for a 20 V output step in less than 100 µs (in the test con- designer to build very high performance, high gain instrumenta- figuration shown in Figure 23). To achieve settling to 18 bits, tion amplifiers without having to select matched op amps for the any amplifier specified to have a gain of 4 V/µV would appear to crucial first stage. For the second stage, the lowest grade AD707 be good enough, however, this is not the case. In order to truly is ideally suited. The CMRR is typically the same as the high achieve 18-bit accuracy, the gain linearity must be better than grade parts, but does not exact a premium for drift performance 4 ppm. (which is less critical in the second stage). Figure 24 shows an The gain nonlinearity of the AD707 does not contribute to the example of the classic instrumentation amp. Figure 25 shows error, and the gain itself only contributes 0.1 ppm. The gain that the circuit has at least 140 dB of common-mode rejection error, along with the V for a ± 10 V common-mode input at a gain of 1001 (RG = 20 Ω). OS and VOS drift errors do not comprise 1 LSB of error in an 18-bit system over the military temperature
20,000
range. If calibration is used to null offset errors, the AD707
CIRCUIT GAIN = –––––– + 1 AD707 RG
resolves up to 20 bits at +25°C.
–IN 3 R4 6 A1 10k
Ω
2 R2 10k
Ω
10k
Ω
AD707 REFERENCE 2 OBSOLETE SIGNAL 10V/Div RG 6 A3 10k
Ω
3 R1 D.U.T. AD707 10k
Ω
OUTPUT 2 9.9k
Ω
ERROR 6 50µV/Div A2 R R2 CM +IN 3 200
Ω
OUTPUT: 10V/Div
Figure 24. A 3 Op Amp Instrumentation Amplifier
TIME – 50µs/Div
High CMRR is obtained by first adjusting RCM until the output does not change as the input is swept through the full common- Figure 22. 18-Bit Settling mode range. The value of RG, should then be selected to achieve the desired gain. Matched resistors should be used for the output stage so that R
2x HP1N6263
CM is as small as possible. The smaller the value Of RCM, the lower the noise introduced by potentiometer
200k
Ω wiper vibrations. To maintain the CMRR at 140 dB over a 20°C range, the resistor ratios in the output stage, R1/R2 and R3/R4, must track each other better than 10 ppm/°C.
2 OP27 6 VERROR x 100 3 7 4 10µF 0.1µF INPUT CH1 COMMON-MODE 10µF 0.1µF SIGNAL: 10V/Div –V +V S S 2k
Ω
2k
Ω
1.9k
Ω
FLAT-TOP PULSE 100
Ω
GENERATOR VIN 2k
Ω
COMMON-MODE 2 ERROR REFERRED DATA CH2 TO INPUT: 5µV/Div DYNAMICS D.U.T. 6 5109 AD707 OR TIME – 2 sec/Div 3 7 EQUIVALENT 4 10µF 0.1µF
Figure 25. Instrumentation Amplifier Common-Mode Rejection
10µF 0.1µF –V +V S S
Figure 23. Op Amp Settling Time Test Circuit REV. B –7–
Figure 22 shows the AD707 settling to within 80 µV of its final The extremely tight dc specifications of the AD707 enable the value for a 20 V output step in less than 100 µs (in the test con- designer to build very high performance, high gain instrumenta- figuration shown in Figure 23). To achieve settling to 18 bits, tion amplifiers without having to select matched op amps for the any amplifier specified to have a gain of 4 V/µV would appear to crucial first stage. For the second stage, the lowest grade AD707 be good enough, however, this is not the case. In order to truly is ideally suited. The CMRR is typically the same as the high achieve 18-bit accuracy, the gain linearity must be better than grade parts, but does not exact a premium for drift performance 4 ppm. (which is less critical in the second stage). Figure 24 shows an The gain nonlinearity of the AD707 does not contribute to the example of the classic instrumentation amp. Figure 25 shows error, and the gain itself only contributes 0.1 ppm. The gain that the circuit has at least 140 dB of common-mode rejection error, along with the V for a ± 10 V common-mode input at a gain of 1001 (RG = 20 Ω). OS and VOS drift errors do not comprise 1 LSB of error in an 18-bit system over the military temperature
20,000
range. If calibration is used to null offset errors, the AD707
CIRCUIT GAIN = –––––– + 1 AD707 RG
resolves up to 20 bits at +25°C.
–IN 3 R4 6 A1 10k
Ω
2 R2 10k
Ω
10k
Ω
AD707 REFERENCE 2 OBSOLETE SIGNAL 10V/Div RG 6 A3 10k
Ω
3 R1 D.U.T. AD707 10k
Ω
OUTPUT 2 9.9k
Ω
ERROR 6 50µV/Div A2 R R2 CM +IN 3 200
Ω
OUTPUT: 10V/Div
Figure 24. A 3 Op Amp Instrumentation Amplifier
TIME – 50µs/Div
High CMRR is obtained by first adjusting RCM until the output does not change as the input is swept through the full common- Figure 22. 18-Bit Settling mode range. The value of RG, should then be selected to achieve the desired gain. Matched resistors should be used for the output stage so that R
2x HP1N6263
CM is as small as possible. The smaller the value Of RCM, the lower the noise introduced by potentiometer
200k
Ω wiper vibrations. To maintain the CMRR at 140 dB over a 20°C range, the resistor ratios in the output stage, R1/R2 and R3/R4, must track each other better than 10 ppm/°C.
2 OP27 6 VERROR x 100 3 7 4 10µF 0.1µF INPUT CH1 COMMON-MODE 10µF 0.1µF SIGNAL: 10V/Div –V +V S S 2k
Ω
2k
Ω
1.9k
Ω
FLAT-TOP PULSE 100
Ω
GENERATOR VIN 2k
Ω
COMMON-MODE 2 ERROR REFERRED DATA CH2 TO INPUT: 5µV/Div DYNAMICS D.U.T. 6 5109 AD707 OR TIME – 2 sec/Div 3 7 EQUIVALENT 4 10µF 0.1µF
Figure 25. Instrumentation Amplifier Common-Mode Rejection
10µF 0.1µF –V +V S S
Figure 23. Op Amp Settling Time Test Circuit REV. B –7–
