Datasheet AOZ5316NQI (Alpha & Omega) - 3
| Manufacturer | Alpha & Omega |
| Description | High-Current, High-Performance DrMOS Power Module |
| Pages / Page | 17 / 3 — AOZ5316NQI. Pin Description. Pin Number. Pin Name. Pin Function. … |
| File Format / Size | PDF / 2.2 Mb |
| Document Language | English |
AOZ5316NQI. Pin Description. Pin Number. Pin Name. Pin Function. www.aosmd.com
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AOZ5316NQI Pin Description Pin Number Pin Name Pin Function
PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be 1 PWM disconnected and this pin will be at high impedance. Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. 2 SMOD# There is an internal pull-down resistor to AGND. 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and 3 VCC AGND (Pin 4). 4 AGND Signal Ground. High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between 5 BOOT BOOT and the PHASE (Pin 7). 6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. 7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). 8, 9, 10, 11 VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET). 12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16,17,18,19, Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side 20,21,22, 23, VSWH MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as 24, 25, 26 main inductor terminal. 27 GL Low-Side MOSFET Gate connection. This is for test purposes only. Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF 28 PGND directly between PGND and PVCC (Pin 29). 5V power rail for High-Side and Low-Side MOSFET gate drivers. Ensure to position a 1µF 29 PVCC MLCC directly between PVCC to PGND (Pin 28). Thermal warning indicator. This is an open-drain output. When the temperature at the driver IC 30 THWN die reaches the Over Temperature Threshold, this pin is pulled low. Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an 31 DISB# internal pull-down resistor to AGND. Rev. 1.0 November 2019
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PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be 1 PWM disconnected and this pin will be at high impedance. Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. 2 SMOD# There is an internal pull-down resistor to AGND. 5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and 3 VCC AGND (Pin 4). 4 AGND Signal Ground. High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between 5 BOOT BOOT and the PHASE (Pin 7). 6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN. 7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5). 8, 9, 10, 11 VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET). 12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET). 16,17,18,19, Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side 20,21,22, 23, VSWH MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as 24, 25, 26 main inductor terminal. 27 GL Low-Side MOSFET Gate connection. This is for test purposes only. Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF 28 PGND directly between PGND and PVCC (Pin 29). 5V power rail for High-Side and Low-Side MOSFET gate drivers. Ensure to position a 1µF 29 PVCC MLCC directly between PVCC to PGND (Pin 28). Thermal warning indicator. This is an open-drain output. When the temperature at the driver IC 30 THWN die reaches the Over Temperature Threshold, this pin is pulled low. Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an 31 DISB# internal pull-down resistor to AGND. Rev. 1.0 November 2019
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Page 3 of 17
