Datasheet ADSP-21566, ADSP-21567, ADSP-21569 (Analog Devices) - 6

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ADSP-21566/21567/21569 SHARC+ CORE ARCHITECTURE 0x FFFF FFFF RESERVED
The ADSP-2156x processors are assembly code compatible with
0x C000 0000
all previous SHARC processors featuring the SHARC or
DMC0 (1GB) 0x 8000 0000
SHARC+ core, beginning with the first generation ADSP-2106x
SPI2/OSPI0 FLASH ADDRESS SPACE (512MB)
SHARC processors and including the ADSP-2116x, ADSP-
0x 6000 0000
2126x, ADSP-213xx, ADSP-214xx, and ADSP-SC5xx/ADSP-
0x 5000 0000
215xx processors.
0x 4C00 0000
The SIMD architecture featured on the ADSP-2156xprocessors
RESERVED
is identical to all previous SIMD SHARC processors, namely the
0x 4800 0000
ADSP-2116x, ADSP-2126x, ADSP-213xx, ADSP-214xx, and
0x 4400 0000
ADSP-SC5xx/ADSP-215xx processors, as shown in Figure 3 and as described in the following sections.
0x 4000 0000 UNIFIED BYTE ADDRESS SP SYSTEM MMR 0x 3000 0000 Single-Instruction, Multiple Data (SIMD) Computational Engine RESERVED
The SHARC+ core contains two computational processing ele- ments that operate as a single-instruction, multiple data (SIMD)
0x 2840 0000
engine.
SHARC1 L1 ADDRESS SPACE VIA SLAVE 1/SLAVE 2 PORTS A 0x 2824 0000 C E
The processing elements are referred to as PEx and PEy, each
RESERVED
containing an arithmetic logic unit (ALU), multiplier, shifter,
0x 202B FFFF
and register file. PEx is always active, and PEy is enabled by set-
0x 2028 0000
ting the PEYEN mode bit in the mode control register
RESERVED
(MODE1).
0x 2011 8000 L2 BOOT ROM 2 (0.25Mb)
SIMD mode allows the processors to execute the same instruc-
0x 2011 0000 L2 BOOT ROM 1 (0.25Mb)
tion in both processing elements, but each processing element
0x 2010 8000
operates on different data. This architecture efficiently executes
L2 BOOT ROM 0 (0.25Mb)
math intensive DSP algorithms. In addition to all the features of
0x 2010 0000 L2 SRAM (8Mb)
previous generation SHARC cores, the SHARC+ core also pro-
0x 2000 0000
vides a new and simpler way to execute an instruction only on
RESERVED 0x 0039 FFFF
the PEy data register.
L1 BLOCK 3 SRAM (1Mb)
SIMD mode also doubles the bandwidth between memory and
0x 0038 0000 ADDRESS SP SHARC PRIV RESERVED
the processing elements, as required for sustained computa-
0x 0031 FFFF
tional operation of two processing elements. When using the
L1 BLOCK 2 SRAM (1Mb) 0x 0030 0000
data address generators (DAGs) to transfer data in SIMD mode,
A A RESERVED C T E E
two data values transfer with each memory or register file
0x 002E FFFF
access.
L1 BLOCK 1 SRAM (1.5Mb) 0x 002C 0000 RESERVED Independent Parallel Computation Units 0x 0026 FFFF L1 BLOCK 0 SRAM (1.5Mb)
Within each processing element is a set of pipelined computa-
0x 0024 0000
tional units. The computational units consist of a multiplier, an
RESERVED/CORE MMRs/ OTHER MEMORY ALIASES 0x 0000 0000
ALU, and a shifter. These units are arranged in parallel, maxi- mizing computational throughput. These computational units Figure 4. ADSP-2156x Memory Map support IEEE 32-bit single-precision floating-point; 40-bit extended-precision floating-point; IEEE 64-bit double-preci- the two data caches. The caches provide user controllable fea- sion floating-point; and 32-bit fixed-point data formats. tures such as full and partial locking, range bound invalidation, A multifunction instruction set supports parallel execution of and flushing. ALU and multiplier operations. In SIMD mode, the parallel
Core Memory-Mapped Registers (CMMR)
ALU and multiplier operations occur in both processing ele- ments per core. The core memory-mapped registers control the L1 instruction and data cache, branch target buffer (BTB), parity error, system All processing operations take one cycle to complete. For all control, debug, and monitor functions. floating-point operations, the processor takes two cycles to complete in case of data dependency. Double-precision float- ing-point data take two to six cycles to complete. The processor stalls for the appropriate number of cycles for an interlocked pipeline plus data dependency check. Rev. 0 | Page 6 of 98 | March 2020 Document Outline System Features Memory Additional Features Applications Table of Contents Revision History General Description SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Error Correcting Code (ECC) Protected L2 Memories Parity Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Octal Serial Peripheral Interface (OSPI) Port Link Port (LP) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator Clock Distribution Unit (CDU) Clock Out/External Clock Booting Power Supplies Power Management Power-Up and Power-Down Sequencing Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Evaluation Board EZ-KIT Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-2156x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 120-Lead LQFP Signal Descriptions GPIO Multiplexing for 120-Lead LQFP ADSP-2156x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Data Transmission Current Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing OSPI Port—Master Timing OSPI0 Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAIx Pin to DAIx Pin Direct Routing (DAI0 Block and DAI1 Block) Up/Down Counter/Rotary Encoder Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-2156x 400-Ball BGA Ball Assignments ADSP-2156x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-2156x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-2156x 120-Lead LQFP Lead Assignments ADSP-2156x 120-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-2156x 120-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 120-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Planned Automotive Production Products Planned Production Products Ordering Guide