Datasheet ADSP-21369 (Analog Devices) - 9

ADSP-21369
The serial ports also contain frame sync error detection logic
Serial Peripheral (Compatible) Interface
where the serial ports detect frame syncs that arrive early (for The processors contain two serial peripheral interface ports example, frame syncs that arrive while the transmission/recep- (SPIs). The SPI is an industry-standard synchronous serial link, tion of the previous word is occurring). All the serial ports also enabling the SPI-compatible port to communicate with other share one dedicated error interrupt. SPI-compatible devices. The SPI consists of two data pins, one
S/PDIF-Compatible Digital Audio Receiver/Transmitter
device select pin, and one clock pin. It is a full-duplex synchronous serial interface, supporting both master and slave The S/PDIF receiver/transmitter has no separate DMA chan- modes. The SPI port can operate in a multimaster environment nels. It receives audio data in serial format and converts it into a by interfacing with up to four other SPI-compatible devices, biphase encoded signal. The serial data input to the either acting as a master or slave device. The SPI-compatible receiver/transmitter can be formatted as left-justified, I2S, or peripheral implementation also features programmable baud right-justified with word widths of 16, 18, 20, or 24 bits. rate and clock phase and polarities. The SPI-compatible port The serial data, clock, and frame sync inputs to the S/PDIF uses open-drain drivers to support a multimaster configuration receiver/transmitter are routed through the signal routing unit and to avoid data contention. (SRU). They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs),
UART Port
or the sample rate converters (SRC) and are controlled by the The processors provide a full-duplex universal asynchronous SRU control registers. receiver/transmitter (UART) port, which is fully compatible with PC-standard UARTs. The UART port provides a simpli-
Synchronous/Asynchronous Sample Rate Converter
fied UART interface to other peripherals or hosts, supporting The sample rate converter (SRC) contains four SRC blocks and full-duplex, DMA-supported, asynchronous transfers of serial is the same core as that used in the AD1896 192 kHz stereo data. The UART also has multiprocessor communication capa- asynchronous sample rate converter and provides up to 128 dB bility using 9-bit address detection. This allows it to be used in SNR. The SRC block is used to perform synchronous or asyn- multidrop networks through the RS-485 data interface chronous sample rate conversion across independent stereo standard. The UART port also includes support for five data bits channels, without using internal processor resources. The four to eight data bits, one stop bit or two stop bits, and none, even, SRC blocks can also be configured to operate together to con- or odd parity. The UART port supports two modes of vert multichannel audio data without phase mismatches. operation: Finally, the SRC can be used to clean up audio data from jittery • PIO (programmed I/O) – The processor sends or receives clock sources such as the S/PDIF receiver. data by writing or reading I/O-mapped UART registers.
Input Data Port
The data is double-buffered on both transmit and receive. The IDP provides up to eight serial input channels—each with • DMA (direct memory access) – The DMA controller trans- its own clock, frame sync, and data inputs. The eight channels fers both transmit and receive data. This reduces the are automatically multiplexed into a single 32-bit by eight-deep number and frequency of interrupts required to transfer FIFO. Data is always formatted as a 64-bit frame and divided data to and from memory. The UART has two dedicated into two 32-bit words. The serial protocol is designed to receive DMA channels, one for transmit and one for receive. These audio channels in I2S, left-justified sample pair, or right-justi- DMA channels have lower default priority than most DMA fied mode. One frame sync cycle indicates one 64-bit left/right channels because of their relatively low service rates. pair, but data is sent to the FIFO as 32-bit words (that is, one- The UART port’s baud rate, serial data format, error code gen- half of a frame at a time). The processor supports 24- and 32-bit eration and status, and interrupts are programmable: I2S, 24- and 32-bit left-justified, and 24-, 20-, 18- and 16-bit • Supporting bit rates ranging from (f /1,048,576) to right-justified formats. SCLK (f /16) bits per second. SCLK
Precision Clock Generators
• Supporting data formats from 7 bits to 12 bits per frame. The precision clock generators (PCG) consist of four units, each • Both transmit and receive operations can be configured to of which generates a pair of signals (clock and frame sync) generate maskable interrupts to the processor. derived from a clock input signal. The units, A B, C, and D, are Where the 16-bit UART_Divisor comes from the DLH register identical in functionality and operate independently of each (most significant eight bits) and DLL register (least significant other. The two signals generated by each unit are normally used eight bits). as a serial bit clock/frame sync pair. In conjunction with the general-purpose timer functions, auto-
Digital Peripheral Interface (DPI)
baud detection is supported. The digital peripheral interface provides connections to two serial peripheral interface ports (SPI), two universal asynchro- nous receiver-transmitters (UARTs), a 2-wire interface (TWI), 12 flags, and three general-purpose timers. Rev. H | Page 9 of 60 | March 2019 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture External Port SDRAM Controller External Memory Shared External Memory External Port Throughput Asynchronous Memory Controller Pulse-Width Modulation Digital Applications Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Synchronous/Asynchronous Sample Rate Converter Input Data Port Precision Clock Generators Digital Peripheral Interface (DPI) Serial Peripheral (Compatible) Interface UART Port Peripheral Timers 2-Wire Interface Port (TWI) I/O Processor Features DMA Controller Delay Line DMA System Design Program Booting Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing Pin to Pin Direct Routing (DAI and DPI) Precision Clock Generator (Direct Pin Routing) Flags SDRAM Interface Timing (166 MHz SDCLK) SDRAM Interface Enable/Disable Timing (166 MHz SDCLK) Memory Read Memory Write Asynchronous Memory Interface (AMI) Enable/Disable Shared Memory Bus Request Serial Ports Input Data Port Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter—Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 256-Ball BGA_ED Pinout 208-Lead LQFP_EP Pinout Package Dimensions Surface-Mount Design Ordering Guide