Datasheet M29W040B (STMicroelectronics) - 2

M29W040B Figure 2. PLCC Connections Figure 3. TSOP Connections
A11 1 32 G CC A9 A10 A12 A15 A16 A18 V W A17 A8 E 1 32 A13 DQ7 A7 A14 A14 DQ6 A6 A13 A17 DQ5 A5 A8 W DQ4 A4 A9 V 8 25 DQ3 A3 9 M29W040B 25 A11 CC M29W040B A18 9 24 V A2 G SS A16 DQ2 A1 A10 A15 DQ1 A0 E A12 DQ0 DQ0 DQ7 17 A7 A0 A6 A1 SS DQ1 DQ2 V DQ3 DQ4 DQ5 DQ6 A5 A2 AI02951 A4 16 17 A3 AI02952
Table 1. Signal Names
Program or Erase commands from modifying the memory. Program and Erase commands are writ- A0-A18 Address Inputs ten to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the DQ0-DQ7 Data Inputs/Outputs process of programming or erasing the memory by taking care of all of the special operations that are E Chip Enable required to update the memory contents. The end G Output Enable of a program or erase operation can be detected and any error conditions identified. The command W Write Enable set required to control the memory is consistent with JEDEC standards. VCC Supply Voltage Chip Enable, Output Enable and Write Enable sig- nals control the bus operation of the memory. VSS Ground They allow simple connection to most micropro- cessors, often without additional logic. The memory is offered in TSOP32 (8 x 20mm),
SUMMARY DESCRIPTION
TSOP32 (8 x 14mm) and PLCC32 packages and The M29W040B is a 4 Mbit (512Kb x8) non-vola- it is supplied with all the bits erased (set to ‘1’). tile memory that can be read, erased and repro- In order to meet environmental requirements, ST grammed. These operations can be performed offers the M29W040B in ECOPACK® packages. using a single low voltage (2.7 to 3.6V) supply. On power-up the memory defaults to its Read mode ECOPACK packages are Lead-free. The category where it can be read in the same way as a ROM or of second Level Interconnect is marked on the EPROM. The M29W040B is fully backward com- package and on the inner box label, in compliance patible with the M29W040. with JEDEC Standard JESD97. The maximum rat- ings related to soldering conditions are also The memory is divided into blocks that can be marked on the inner box label. erased independently so it is possible to preserve valid data while old data is erased. Each block can ECOPACK is an ST trademark. ECOPACK speci- be protected independently to prevent accidental fications are available at: www.st.com. 2/20 Document Outline Table 1. Signal Names Table 2. Absolute Maximum Ratings (1) Table 3. Uniform Block Addresses, M29W040B Table 4. Bus Operations Table 5. Commands Read/Reset. Auto Select. Program, Unlock Bypass Program, Chip Erase, Block Erase. Unlock Bypass. Unlock Bypass Reset. Erase Suspend. Erase Resume. Table 6. Program, Erase Times and Program, Erase Endurance Cycles (TA = 0 to 70˚C or –40 to 85˚C) Table 7. Status Register Bits Table 8. AC Measurement Conditions Table 9. Capacitance (TA = 25 ˚C, f = 1 MHz) Table 10. DC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 11. Read AC Characteristics (TA = 0 to 70˚C or –40 to 85˚C) Table 12. Write AC Characteristics, Write Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 13. Write AC Characteristics, Chip Enable Controlled (TA = 0 to 70˚C or –40 to 85˚C) Table 14. Ordering Information Scheme Table 15. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Mechanical Data Table 16. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Mechanical Data Table 17. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Mechanical Data Table 18. Revision History SUMMARY DESCRIPTION SIGNAL DESCRIPTIONS Address Inputs (A0-A18). Data Inputs/Outputs (DQ0-DQ7). Chip Enable (E). Output Enable (G). Write Enable (W). VCC Supply Voltage. VSS Ground. BUS OPERATIONS Bus Read. Bus Write. Output Disable. Standby. Automatic Standby. Special Bus Operations Electronic Signature. Block Protection and Blocks Unprotection. COMMAND INTERFACE Read/Reset Command. Auto Select Command. Program Command. Unlock Bypass Command. Unlock Bypass Program Command. Unlock Bypass Reset Command. Chip Erase Command. Block Erase Command. Erase Suspend Command. Erase Resume Command. STATUS REGISTER Data Polling Bit (DQ7). Toggle Bit (DQ6). Error Bit (DQ5). Erase Timer Bit (DQ3). Alternative Toggle Bit (DQ2). Figure 1. Logic Diagram Figure 2. PLCC Connections Figure 3. TSOP Connections Figure 4. Data Polling Flowchart Figure 5. Data Toggle Flowchart Figure 6. AC Testing Input Output Waveform Figure 7. AC Testing Load Circuit Figure 8. Read Mode AC Waveforms Figure 9. Write AC Waveforms, Write Enable Controlled Figure 10. Write AC Waveforms, Chip Enable Controlled Figure 11. PLCC32 – 32 lead Plastic Leaded Chip Carrier, Package Outline Figure 12. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 20mm, Package Outline Figure 13. TSOP32 – 32 lead Plastic Thin Small Outline, 8 x 14mm, Package Outline