Datasheet LTC1960 (Analog Devices) - 5

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ELECTRICAL CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range (Note 7), otherwise specifications are at TA = 25°C. VDCIN = 20V, VBAT1 = 12V, VBAT2 = 12V, unless otherwise noted. SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
tONPI Gate B1I/B2I/DCI Turn-On Time VGS < –3V, CLOAD = 3nF (Note 5) 300 µs tOFFPI Gate B1I/B2I/DCI Turn-Off Time VGS > –1V, CLOAD = 3nF (Note 5) 10 µs VPONI Input Gate Clamp Voltage ILOAD = 1µA GB1I Highest (VBAT1 or VSCP) – VGB1I 4.75 6.7 7.5 V GB2I Highest (VBAT2 or VSCP) – VGB2I 4.75 6.7 7.5 V GDCI Highest (VDCIN or VSCP) – VGDCI 4.75 6.7 7.5 V VPOFFI Input Gate Off Voltage ILOAD = 25µA GB1I Highest (VBAT1 or VSCP) – VGB1I 0.18 0.25 V GB2I Highest (VBAT2 or VSCP) – VGB2I 0.18 0.25 V GDCI Highest (VDCIN or VSCP) – VGDCI 0.18 0.25 V
Logic I/O
IIH/IIL SSB/SCK/MOSI Input High/Low Current l –1 1 µA VIL SSB/MOSI/SCK Input Low Voltage l 0.8 V VIH SSB/MOSI/SCK Input High Voltage l 2 V VOL MISO Output Low Voltage IOL = 1.3mA l 0.4 V IOFF MISO Output Off-State Leakage Current VMISO = 5V l 2 µA
SPI Timing (See Timing Diagram)
TWD Watch Dog Timer l 1.2 2.5 4.5 sec tSSH SSB High Time 680 ns tCYC SCK Period CLOAD = 200pF RPULLUP = 4.7k on MISO l 2 µs tSH SCK High Time 680 ns tSL SCK Low Time 680 ns tLD Enable Lead Time 200 ns tLG Enable Lag Time 200 ns tsu Input Data Set-Up Time l 100 ns tH Input Data Hold Time l 100 ns tA Access Time (From Hi-Z to Data Active on MISO) l 125 ns tdis Disable Time (Hold Time to Hi-Z State on MISO) l 125 ns tV Output Data Valid CL = 200pF, RPULLUP = 4.7k on MISO l 580 ns tHO Output Data Hold l 0 ns tIr SCK/MOSI/SSB Rise Time 0.8V to 2V 250 ns tIf SCK/MOSI/SSB Fall Time 2V to 0.8V 250 ns tOf MISO Fall Time 2V to 0.4V, CL = 200pF l 400 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings GB1I and GB2I. SCP is set at 11.9V to measure sink current at GDCI, GB1I may cause permanent damage to the device. Exposure to any Absolute and GB2I. Maximum Rating condition for extended periods may affect device
Note 5.
Extrapolated from testing with CL = 50pF. reliability and lifetime.
Note 6.
VDAC offset is equal to the reference voltage, since
Note 2.
Battery voltage must be adequate to drive gates of PowerPath V P-channel FET switches. This does not affect charging voltage of the OUT = VREF(16mV • VDAC(VALUE)/2047 + 1) battery, which can be zero volts.
Note 7.
The LTC1960C is guaranteed to meet specified performance from 0°C to 70°C and is designed, characterized and expected to meet specified
Note 3.
See Test Circuit. performance at –40°C and 85°C, but is not tested at these extended
Note 4
. DCIN, BAT1, BAT2 are held at 12V and GDCI, GB1I, GB2I are temperature limits. forced to 10.5V. SCP is set at 12.0V to measure source current at GDCI,
Note 8.
Does not apply to low current mode. Refer to “The Current DAC Block” in the Operation section. Rev. C For more information www.analog.com 5 Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Pin Configuration Order Information Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Test Circuit Timing Diagram Operation Applications Information Package Description Revision History Typical Application Related Parts