Datasheet AD8023 (Analog Devices) - 10

AD8023 RF +V 1.0 F S 0.1 F R V G IN 4 15 AD8023 V 1.0 F O R 11 V S C IN L 0.1 F RT –VS V
Figure 31. Circuit for Driving a Capacitive Load
O Table II. Recommended Feedback and Series Resistors vs. Capacitive Load and Gain
Figure 33. 50% Overload Recovery, Gain = +10, (RF = 300 Ω, RL = 1 kΩ, VS = ±7.5 V)
RS – Ohms C
As noted in the warning under Maximum Power Dissipation, a
L – pF RF – Ohms G = 2 G
≥
3
high level of input overdrive in a high noninverting gain circuit 20 2k 0 0 can result in a large current flow in the input stage. Though this 50 2k 10 10 current is internally limited to about 30 mA, its effect on the 100 2k 15 15 200 3k 10 10 total power dissipation may be significant. 300 3k 10 10
Disable Mode Operation
≥500 3k 10 10 Pulling the voltage on any one of the Disable pins about 1.6 V up from the negative supply will put the corresponding amplifier into a disabled, powered down, state. In this condition, the amplifier’s quiescent current drops to about 1.3 mA, its output becomes a high impedance, and there is a high level of isolation from input to output. In the case of a gain of two line driver for example, the impedance at the output node will be about the same as for a 1.5 kΩ resistor (the feedback plus gain resistors) in parallel with a 12 pF capacitor.
VIN
Leaving the Disable pin disconnected (floating) will leave the corresponding amplifier operational, in the enabled state. The input impedance of the disable pin is about 25 kΩ in parallel with a few picofarads. When driven to 0 V, with the negative supply at –7.5 V, about 100 µA flows into the disable pin.
VO
When the disable pins are driven by complementary output CMOS logic, on a single 5 V supply, the disable and enable times are about 50 ns. When operated on dual supplies, level Figure 32. Pulse Response Driving a Large Load Capacitor. shifting will be required from standard logic outputs to the Disable pins. Figure 33 shows one possible method, which CL = 300 pF, G = +3, RF = 750 Ω, RS = 16.9 Ω, RL = 10 kΩ results in a negligible increase in switching time.
Overload Recovery
The three important overload conditions are: input common-
+5
mode voltage overdrive, output voltage overdrive, and input
VI +7.5V
current overdrive. When configured for a low closed-loop gain, this amplifier will quickly recover from an input common-mode
15k
voltage overdrive; typically in under 25 ns. When configured for a higher gain, and overloaded at the output, the recovery time
TO DISABLE PIN
will also be short. For example, in a gain of +10, with 50%
4k 10k
overdrive, the recovery time of the AD8023 is about 20 ns (see
–7.5V
Figure 31). For higher overdrive, the response is somewhat
VI HIGH => AMPLIFIER ENABLED
slower. For 100% overdrive, (in a gain of +10), the recovery
VI LOW => AMPLIFIER DISABLED
time is about 80 ns. Figure 34. Level Shifting to Drive Disable Pins on Dual Supplies The AD8023’s input stages include protection from the large differential input voltages that may be applied when disabled. Internal clamps limit this voltage to about ±3 V. The high input to output isolation will be maintained for voltages below this limit. –10– REV. A