Datasheet PIC16F8X: PIC16F83, PIC16F84, PIC16CR83, PIC16CR84 (Microchip) - 10
| Manufacturer | Microchip |
| Description | 18-pin Flash/EEPROM 8-Bit Microcontrollers |
| Pages / Page | 128 / 10 — PIC16F8X. 3.1. Clocking Scheme/Instruction Cycle. 3.2. Instruction … |
| File Format / Size | PDF / 1.8 Mb |
| Document Language | English |
PIC16F8X. 3.1. Clocking Scheme/Instruction Cycle. 3.2. Instruction Flow/Pipelining. FIGURE 3-2:. CLOCK/INSTRUCTION CYCLE
Model Line for this Datasheet
Text Version of Document
PIC16F8X 3.1 Clocking Scheme/Instruction Cycle 3.2 Instruction Flow/Pipelining
The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1, four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle program counter (PC) is incremented every Q1, the while decode and execute takes another instruction instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. The effectively executes in one cycle. If an instruction instruction is decoded and executed during the causes the program counter to change (e.g., GOTO) following Q1 through Q4. The clocks and instruction then two cycles are required to complete the instruction execution flow is shown in Figure 3-2. (Example 3-1). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30430D-page 10 1996-2013 Microchip Technology Inc.
The clock input (from OSC1) is internally divided by An “Instruction Cycle” consists of four Q cycles (Q1, four to generate four non-overlapping quadrature Q2, Q3 and Q4). The instruction fetch and execute are clocks namely Q1, Q2, Q3 and Q4. Internally, the pipelined such that fetch takes one instruction cycle program counter (PC) is incremented every Q1, the while decode and execute takes another instruction instruction is fetched from the program memory and cycle. However, due to the pipelining, each instruction latched into the instruction register in Q4. The effectively executes in one cycle. If an instruction instruction is decoded and executed during the causes the program counter to change (e.g., GOTO) following Q1 through Q4. The clocks and instruction then two cycles are required to complete the instruction execution flow is shown in Figure 3-2. (Example 3-1). A fetch cycle begins with the Program Counter (PC) incrementing in Q1. In the execution cycle, the fetched instruction is latched into the “Instruction Register” in cycle Q1. This instruction is then decoded and executed during the Q2, Q3, and Q4 cycles. Data memory is read during Q2 (operand read) and written during Q4 (destination write).
FIGURE 3-2: CLOCK/INSTRUCTION CYCLE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 OSC1 Q1 Q2 Internal phase Q3 clock Q4 PC PC PC+1 PC+2 OSC2/CLKOUT (RC mode) Fetch INST (PC) Execute INST (PC-1) Fetch INST (PC+1) Execute INST (PC) Fetch INST (PC+2) Execute INST (PC+1)
EXAMPLE 3-1: INSTRUCTION PIPELINE FLOW
1. MOVLW 55h Fetch 1 Execute 1 2. MOVWF PORTB Fetch 2 Execute 2 3. CALL SUB_1 Fetch 3 Execute 3 4. BSF PORTA, BIT3 Fetch 4 Flush Fetch SUB_1 Execute SUB_1 All instructions are single cycle, except for any program branches. These take two cycles since the fetch instruction is “flushed” from the pipeline while the new instruction is being fetched and then executed. DS30430D-page 10 1996-2013 Microchip Technology Inc.
