Datasheet ADP1878, ADP1879 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | Synchronous Buck Controller with Constant On-Time and Valley Current Mode with Power Saving Mode |
| Pages / Page | 40 / 6 — ADP1878/ADP1879. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. … |
| Revision | B |
| File Format / Size | PDF / 2.0 Mb |
| Document Language | English |
ADP1878/ADP1879. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VIN 1. BST. COMP 2. EN 3. DRVH. FB 4. PGND. GND 5. DRVL. RES 6. PGOOD
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ADP1878/ADP1879 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP1878/ADP1879 VIN 1 14 BST COMP 2 13 SW EN 3 12 DRVH FB 4 11 PGND GND 5 10 DRVL RES 6 9 PGOOD VREG 7 8 SS TOP VIEW (Not to Scale)
3
NOTES
00 1-
1. CONNECT THE EXPOSED PAD TO THE
44
ANALOG GROUND PIN (GND).
09 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET. 2 COMP Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see the Compensation Network section). 3 EN IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC. 4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 5 GND Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout Considerations section). 6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). 7 VREG Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers). Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are recommended. 8 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value of 10 nF for every 1 ms of soft start delay. 9 PGOOD Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown. Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used. 10 DRVL Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin (see Figure 69). 11 PGND Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET. 12 DRVH Drive Output for the External High-Side N-Channel MOSFET. 13 SW Switch Node Connection. 14 BST Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. EP Exposed Pad. Connect the exposed pad to the analog ground pin (GND). Rev. B | Page 6 of 40 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Diagram Startup Soft Start Precision Enable Circuitry Undervoltage Lockout On-Board Low Dropout (LDO) Regulator Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier ADP1879 Power Saving Mode (PSM) Timer Operation Pseudo Fixed Frequency Power-Good Monitoring Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (Gm) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Consideration Channel Conduction Loss MOSFET Driver Loss MOSFET Switching Loss Body Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current-Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Application Circuits 12 A, 300 kHz High Current Application Circuit 5.5 V Input, 600 kHz Current Application Circuit 300 kHz High Current Application Circuit Packaging and Ordering Information Outline Dimensions Ordering Guide
ADP1878/ADP1879 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADP1878/ADP1879 VIN 1 14 BST COMP 2 13 SW EN 3 12 DRVH FB 4 11 PGND GND 5 10 DRVL RES 6 9 PGOOD VREG 7 8 SS TOP VIEW (Not to Scale)
3
NOTES
00 1-
1. CONNECT THE EXPOSED PAD TO THE
44
ANALOG GROUND PIN (GND).
09 Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN High-Side Input Voltage. Connect VIN to the drain of the high-side MOSFET. 2 COMP Output of the Error Amplifier. Connect compensation network between this pin and AGND to achieve stability (see the Compensation Network section). 3 EN IC Enable. Connect EN to VREG to enable the IC. When pulled down to AGND externally, EN disables the IC. 4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 5 GND Analog Ground Reference Pin of the IC. Connect all sensitive analog components to this ground plane (see the Layout Considerations section). 6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). 7 VREG Internal Regulator Supply Bias Voltage for the ADP1878/ADP1879 Controller (Includes the Output Gate Drivers). Connecting a bypass capacitor of 1 μF directly from this pin to PGND and a 0.1 μF capacitor across VREG and GND are recommended. 8 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. There is a capacitance value of 10 nF for every 1 ms of soft start delay. 9 PGOOD Open-Drain Power-Good Output. PGOOD sinks current when FB is out of regulation or during thermal shutdown. Connect a 3 kΩ resistor between PGOOD and VREG. Leave PGOOD unconnected if it is not used. 10 DRVL Drive Output for the External Low-Side, N-Channel MOSFET. This pin also serves as the current sense gain setting pin (see Figure 69). 11 PGND Power Ground. Ground for the low-side gate driver and low-side N-channel MOSFET. 12 DRVH Drive Output for the External High-Side N-Channel MOSFET. 13 SW Switch Node Connection. 14 BST Bootstrap for the High-Side N-Channel MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. EP Exposed Pad. Connect the exposed pad to the analog ground pin (GND). Rev. B | Page 6 of 40 Document Outline Features Applications Typical Applications Circuit General Description Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Block Diagram Startup Soft Start Precision Enable Circuitry Undervoltage Lockout On-Board Low Dropout (LDO) Regulator Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier ADP1879 Power Saving Mode (PSM) Timer Operation Pseudo Fixed Frequency Power-Good Monitoring Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (Gm) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Consideration Channel Conduction Loss MOSFET Driver Loss MOSFET Switching Loss Body Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current-Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Application Circuits 12 A, 300 kHz High Current Application Circuit 5.5 V Input, 600 kHz Current Application Circuit 300 kHz High Current Application Circuit Packaging and Ordering Information Outline Dimensions Ordering Guide
