Datasheet ADP1874, ADP1875 (Analog Devices) - 7

ManufacturerAnalog Devices
DescriptionSynchronous Buck Controller with Constant On-Time, Valley Current Mode, and Power Saving Mode
Pages / Page44 / 7 — Data Sheet. ADP1874/ADP1875. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. …
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File Format / SizePDF / 1.8 Mb
Document LanguageEnglish

Data Sheet. ADP1874/ADP1875. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VIN. 16 BST. COMP. 15 SW. 14 DRVH. ADP1874/. ADP1875. 13 PGND. GND

Data Sheet ADP1874/ADP1875 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 16 BST COMP 15 SW 14 DRVH ADP1874/ ADP1875 13 PGND GND

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Data Sheet ADP1874/ADP1875 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN 1 16 BST COMP 2 15 SW EN 3 14 DRVH ADP1874/ FB 4 ADP1875 13 PGND GND 5 TOP VIEW 12 DRVL (Not to Scale) RES 6 11 PGOOD VREG 7 10 SS
003
VREG_IN 8 9 TRACK
09347- Figure 3. Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
1 VIN High-Side Input Voltage. Connect VIN to the drain of the upper side MOSFET. 2 COMP Output of the Error Amplifier. Connect the compensation network between this pin and AGND to achieve stability (see the Compensation Network section). 3 EN Connect to VREG to Enable IC. When pulled down to AGND externally, disables the IC. 4 FB Noninverting Input of the Internal Error Amplifier. This is the node where the feedback resistor is connected. 5 GND Analog Ground Reference Pin of the IC. All sensitive analog components should be connected to this ground plane (see the Layout Considerations section). 6 RES Current Sense Gain Resistor (External). Connect a resistor between the RES pin and GND (Pin 5). 7 VREG Internal Regulator Supply Bias Voltage for the ADP1874/ADP1875 Controller (Includes the Output Gate Drivers). A bypass capacitor of 1 µF directly from this pin to PGND and a 0.1 µF across VREG and GND are recommended. 8 VREG_IN Input to the Internal LDO. Tie this pin directly to Pin 7 (VREG). 9 TRACK Tracking Input. If the tracking function is not used, it is recommended to connect TRACK to VREG through a resistor higher than 1 MΩ or simply connect TRACK between 0.7 V and 2 V to reduce the bias current going into the pin. 10 SS Soft Start Input. Connect an external capacitor to GND to program the soft start period. Capacitance value of 10 nF for every 1 ms of soft start delay. 11 PGOOD Open-Drain Power Good Output. Sinks current when FB is out of regulation or during thermal shutdown. Connect a 3 kΩ resistor between PGOOD and VREG. Leave unconnected if not used. 12 DRVL Drive Output for the External Lower Side, N-Channel MOSFET. This pin also serves as the current-sense gain setting pin (see Figure 69). 13 PGND Power GND. Ground for the lower side gate driver and lower side, N-channel MOSFET. 14 DRVH Drive Output for the External Upper Side, N-Channel MOSFET. 15 SW Switch Node Connection. 16 BST Bootstrap for the Upper Side MOSFET Gate Drive Circuitry. An internal boot rectifier (diode) is connected between VREG and BST. A capacitor from BST to SW is required. An external Schottky diode can also be connected between VREG and BST for increased gate drive capability. Rev. A | Page 7 of 44 Document Outline Features Applications General Description Typical Applications Circuit Table of Contents Revision History Specifications Absolute Maximum Ratings Thermal Resistance Boundary Condition ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics ADP1874/ADP1875 Block Digram Theory of Operation Startup Soft Start Precision Enable Circuitry Undervoltage Lockout On-Board Low Dropout Regulator Thermal Shutdown Programming Resistor (RES) Detect Circuit Valley Current-Limit Setting Hiccup Mode During Short Circuit Synchronous Rectifier ADP1875 Power Saving Mode (PSM) Timer Operation Pseudo-Fixed Frequency Power Good Monitoring Voltage Tracking Applications Information Feedback Resistor Divider Inductor Selection Output Ripple Voltage (ΔVRR) Output Capacitor Selection Compensation Network Output Filter Impedance (ZFILT) Error Amplifier Output Impedance (ZCOMP) Error Amplifier Gain (Gm) Current-Sense Loop Gain (GCS) Crossover Frequency Efficiency Consideration Channel Conduction Loss MOSFET Driver Loss Switching Loss Diode Conduction Loss Inductor Loss Input Capacitor Selection Thermal Considerations Design Example Input Capacitor Inductor Current Limit Programming Output Capacitor Feedback Resistor Network Setup Compensation Network Loss Calculations External Component Recommendations Layout Considerations IC Section (Left Side of Evaluation Board) Power Section Differential Sensing Typical Application Circuits 12 A, 300 kHz High Current Application Circuit 5.5 V Input, 600 kHz Application Circuit 300 kHz High Current Application Circuit Outline Dimensions Ordering Guide