Datasheet HT68F2420 (Holtek) - 9
| Manufacturer | Holtek |
| Description | High Precision HIRC Flash MCU |
| Pages / Page | 70 / 9 — HT68F2420. High Precision HIRC Flash MCU. A.C. Characteristics. Internal … |
| File Format / Size | PDF / 1.2 Mb |
| Document Language | English |
HT68F2420. High Precision HIRC Flash MCU. A.C. Characteristics. Internal Oscillator Characteristics. Test Conditions. Symbol
Model Line for this Datasheet
Text Version of Document
HT68F2420 HT68F2420 High Precision HIRC Flash MCU High Precision HIRC Flash MCU A.C. Characteristics
For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an influence on the measured values.
Internal Oscillator Characteristics
Ta=25°C Typical, unless otherwise specified
Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Temp.
3V 25°C -0.4% 4 -0.4% -10°C to 50°C -0.8% 4 -0.8% 2.2V~3.6V -40°C to 85°C -1.5% 4 +1.5% -10°C to 50°C -0.8% 4 +0.8% f HIRC requency HIRC (System Frequency) 1.8V~3.6V MHz -40°C to 85°C -1.5% 4 +1.5% -10°C to 50°C -0.8% 4 +0.8% 2.2V~5.5V -40°C to 85°C -1.5% 4 +1.5% 1.8V~5.5V -40°C to 85°C -1.5% 4 +1.5% 5V 25°C 25.6 32 38.4 fLIRC LIRC Frequency 25°C 12.8 32 41.6 kHz 1.8V~5.5V -40°C ~ 85°C 8 32 60 tSTART LIRC Start Up Time — — — — 100 μs
System Start Up Time Characteristics
Ta=25°C Typical
Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions
System Start-up Time fSYS=fH~fH/64, fH=fHIRC — 16 — tHIRC Wake-up from condition where fSYS is off fSYS=fSUB=fLIRC — 2 — tLIRC System Start-up Time fSYS=fH~fH/64, fH=fHIRC — 2 — tH tSST Wake-up from condition where fSYS is on — fSYS=fSUB=fLIRC — 2 — tSUB System Speed Switch Time FAST to SLOW Mode or SLOW to FAST fHIRC switches from off → on — 16 — tHIRC Mode System Reset Delay Time Reset source from Power-on reset or RRPOR=5V/ms LVR Hardware Reset tRSTD System Reset Delay Time — 8 16 60 ms WDTC/LVRC software reset — System Reset Delay Time Reset source from WDT overflow — tSRESET Minimum software reset width to reset — — 45 90 375 μs Note: 1. For the System Start-up time values, whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator. Details are provided in the System Operating Modes section. 2. tLIRC=1/fLIRC 3. If the LIRC is used as the system clock and if it is off when in the SLEEP Mode, then an additional LIRC start up time, tSTART, as provided in the LIRC frequency table, must be added to the tSST time in the table above. 4. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up. Rev. 1.00 8 October 08, 2020 Rev. 1.00 9 October 08, 2020 Document Outline Features CPU Features Peripheral Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics Operating Voltage Characteristics Operating Current Characteristics Standby Current Characteristics A.C. Characteristics Internal Oscillator Characteristics System Start Up Time Characteristics Input/Output Characteristics REM/REMDRV Pin Characteristics LVR Electrical Characteristics Power on Reset Characteristics System Architecture Clocking and Pipelining Program Counter Stack Arithmetic and Logic Unit – ALU Flash Program Memory Structure Special Vectors Look-up Table Table Program Example In Circuit Programming – ICP On-Chip Debug Support – OCDS Data Memory Structure General Purpose Data Memory Special Purpose Data Memory Special Function Register Description Indirect Addressing Registers – IAR0 Memory Pointers – MP0 Accumulator – ACC Program Counter Low Register – PCL Look-up Table Registers – TBLP, TBLH Status Register – STATUS Oscillators Oscillator Overview System Clock Configurations Internal RC Oscillator – HIRC Internal 32kHz Oscillator – LIRC Operating Modes and System Clocks System Clocks System Operation Modes Control Register Operating Mode Switching Standby Current Considerations Wake-up Watchdog Timer Watchdog Timer Clock Source Watchdog Timer Control Register Watchdog Timer Operation Reset and Initialisation Reset Functions Reset Initial Conditions Input/Output Ports Pull-high Resistors I/O Pin Wake-up I/O Port Control Registers I/O Pin Structures Programming Considerations 9-bit Timer with Carrier Output Timer and Carrier Output Conctrol Register Timer Operation Carrier Output Carrier Output Pins Interrupts Interrupt Register Interrupt Operation Time Base Interrupt Interrupt Wake-up Function Programming Considerations Application Circuits Instruction Set Introduction Instruction Timing Moving and Transferring Data Arithmetic Operations Logical and Rotate Operation Branches and Control Transfer Bit Operations Table Read Operations Other Operations Instruction Set Summary Table Conventions Instruction Definition Package Information 8-pin SOP (150mil) Outline Dimensions 16-pin NSOP (150mil) Outline Dimensions 20-pin NSOP (150mil) Outline Dimensions 20-pin SSOP (150mil) Outline Dimensions
For data in the following tables, note that factors such as oscillator type, operating voltage, operating frequency and temperature etc., can all exert an influence on the measured values.
Internal Oscillator Characteristics
Ta=25°C Typical, unless otherwise specified
Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Temp.
3V 25°C -0.4% 4 -0.4% -10°C to 50°C -0.8% 4 -0.8% 2.2V~3.6V -40°C to 85°C -1.5% 4 +1.5% -10°C to 50°C -0.8% 4 +0.8% f HIRC requency HIRC (System Frequency) 1.8V~3.6V MHz -40°C to 85°C -1.5% 4 +1.5% -10°C to 50°C -0.8% 4 +0.8% 2.2V~5.5V -40°C to 85°C -1.5% 4 +1.5% 1.8V~5.5V -40°C to 85°C -1.5% 4 +1.5% 5V 25°C 25.6 32 38.4 fLIRC LIRC Frequency 25°C 12.8 32 41.6 kHz 1.8V~5.5V -40°C ~ 85°C 8 32 60 tSTART LIRC Start Up Time — — — — 100 μs
System Start Up Time Characteristics
Ta=25°C Typical
Test Conditions Symbol Parameter Min. Typ. Max. Unit VDD Conditions
System Start-up Time fSYS=fH~fH/64, fH=fHIRC — 16 — tHIRC Wake-up from condition where fSYS is off fSYS=fSUB=fLIRC — 2 — tLIRC System Start-up Time fSYS=fH~fH/64, fH=fHIRC — 2 — tH tSST Wake-up from condition where fSYS is on — fSYS=fSUB=fLIRC — 2 — tSUB System Speed Switch Time FAST to SLOW Mode or SLOW to FAST fHIRC switches from off → on — 16 — tHIRC Mode System Reset Delay Time Reset source from Power-on reset or RRPOR=5V/ms LVR Hardware Reset tRSTD System Reset Delay Time — 8 16 60 ms WDTC/LVRC software reset — System Reset Delay Time Reset source from WDT overflow — tSRESET Minimum software reset width to reset — — 45 90 375 μs Note: 1. For the System Start-up time values, whether fSYS is on or off depends upon the mode type and the chosen fSYS system oscillator. Details are provided in the System Operating Modes section. 2. tLIRC=1/fLIRC 3. If the LIRC is used as the system clock and if it is off when in the SLEEP Mode, then an additional LIRC start up time, tSTART, as provided in the LIRC frequency table, must be added to the tSST time in the table above. 4. The System Speed Switch Time is effectively the time taken for the newly activated oscillator to start up. Rev. 1.00 8 October 08, 2020 Rev. 1.00 9 October 08, 2020 Document Outline Features CPU Features Peripheral Features General Description Block Diagram Pin Assignment Pin Description Absolute Maximum Ratings D.C. Characteristics Operating Voltage Characteristics Operating Current Characteristics Standby Current Characteristics A.C. Characteristics Internal Oscillator Characteristics System Start Up Time Characteristics Input/Output Characteristics REM/REMDRV Pin Characteristics LVR Electrical Characteristics Power on Reset Characteristics System Architecture Clocking and Pipelining Program Counter Stack Arithmetic and Logic Unit – ALU Flash Program Memory Structure Special Vectors Look-up Table Table Program Example In Circuit Programming – ICP On-Chip Debug Support – OCDS Data Memory Structure General Purpose Data Memory Special Purpose Data Memory Special Function Register Description Indirect Addressing Registers – IAR0 Memory Pointers – MP0 Accumulator – ACC Program Counter Low Register – PCL Look-up Table Registers – TBLP, TBLH Status Register – STATUS Oscillators Oscillator Overview System Clock Configurations Internal RC Oscillator – HIRC Internal 32kHz Oscillator – LIRC Operating Modes and System Clocks System Clocks System Operation Modes Control Register Operating Mode Switching Standby Current Considerations Wake-up Watchdog Timer Watchdog Timer Clock Source Watchdog Timer Control Register Watchdog Timer Operation Reset and Initialisation Reset Functions Reset Initial Conditions Input/Output Ports Pull-high Resistors I/O Pin Wake-up I/O Port Control Registers I/O Pin Structures Programming Considerations 9-bit Timer with Carrier Output Timer and Carrier Output Conctrol Register Timer Operation Carrier Output Carrier Output Pins Interrupts Interrupt Register Interrupt Operation Time Base Interrupt Interrupt Wake-up Function Programming Considerations Application Circuits Instruction Set Introduction Instruction Timing Moving and Transferring Data Arithmetic Operations Logical and Rotate Operation Branches and Control Transfer Bit Operations Table Read Operations Other Operations Instruction Set Summary Table Conventions Instruction Definition Package Information 8-pin SOP (150mil) Outline Dimensions 16-pin NSOP (150mil) Outline Dimensions 20-pin NSOP (150mil) Outline Dimensions 20-pin SSOP (150mil) Outline Dimensions
