Datasheet SLG47004 (Dialog Semiconductor) - 7
| Manufacturer | Dialog Semiconductor |
| Description | GreenPAK Programmable Mixed-Signal Matrix with In-System Programmability and Advanced Analog Features |
| Pages / Page | 243 / 7 — SLG47004. Preliminary. Datasheet. Revision 2.1. 13-Nov-2020 |
| File Format / Size | PDF / 5.6 Mb |
| Document Language | English |
SLG47004. Preliminary. Datasheet. Revision 2.1. 13-Nov-2020
Model Line for this Datasheet
Text Version of Document
link to page 139 link to page 139 link to page 140 link to page 143 link to page 144 link to page 145 link to page 146 link to page 148 link to page 149 link to page 150 link to page 151 link to page 152 link to page 154 link to page 155 link to page 156 link to page 157 link to page 158 link to page 158 link to page 159 link to page 159 link to page 160 link to page 160 link to page 161 link to page 166 link to page 168 link to page 169 link to page 173 link to page 174
SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features Figure 113: Programmable Delay ..140 Figure 114: Edge Detector Output ...140 Figure 115: Deglitch Filter or Edge Detector..141 Figure 116: Generalized Vref Structure..144 Figure 117: ACMP0L, ACMP1L Voltage Reference Block Diagram ..145 Figure 118: HD Buffer and Chopper ACMP Reference Block Diagram ...146 Figure 119: Operational Amplifiers Voltage Reference Block Diagram..147 Figure 120: Oscillator0 Block Diagram...149 Figure 121: Oscillator1 Block Diagram...150 Figure 122: Oscillator2 Block Diagram...151 Figure 123: Clock Scheme...152 Figure 124: Oscillator Startup Diagram..153 Figure 125: POR Sequence ...155 Figure 126: Internal Macrocel States During POR Sequence...156 Figure 127: Power-Down..157 Figure 128: Basic Command Structure ..158 Figure 129: I2C General Timing Characteristics...159 Figure 130: Byte Write Command, R/W = 0...159 Figure 131: Sequential Write Command ..160 Figure 132: Current Address Read Command, R/W = 1..160 Figure 133: Random Read Command ...161 Figure 134: Sequential Read Command..161 Figure 135: Reset Command Timing ...162 Figure 136: Example of I2C Byte Write Bit Masking...167 Figure 137: Page Write Command...169 Figure 138: I2C Block Addressing ..170 Figure 139: Analog Temperature Sensor Structure Diagram...174 Figure 140: TS Output vs. Temperature, VDD = 3.3 V ...175
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 7 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History
SLG47004
GreenPAK Programmable Mixed-Signal Matrix
Preliminary
with In-System Programmability and Advanced Analog Features Figure 113: Programmable Delay ..140 Figure 114: Edge Detector Output ...140 Figure 115: Deglitch Filter or Edge Detector..141 Figure 116: Generalized Vref Structure..144 Figure 117: ACMP0L, ACMP1L Voltage Reference Block Diagram ..145 Figure 118: HD Buffer and Chopper ACMP Reference Block Diagram ...146 Figure 119: Operational Amplifiers Voltage Reference Block Diagram..147 Figure 120: Oscillator0 Block Diagram...149 Figure 121: Oscillator1 Block Diagram...150 Figure 122: Oscillator2 Block Diagram...151 Figure 123: Clock Scheme...152 Figure 124: Oscillator Startup Diagram..153 Figure 125: POR Sequence ...155 Figure 126: Internal Macrocel States During POR Sequence...156 Figure 127: Power-Down..157 Figure 128: Basic Command Structure ..158 Figure 129: I2C General Timing Characteristics...159 Figure 130: Byte Write Command, R/W = 0...159 Figure 131: Sequential Write Command ..160 Figure 132: Current Address Read Command, R/W = 1..160 Figure 133: Random Read Command ...161 Figure 134: Sequential Read Command..161 Figure 135: Reset Command Timing ...162 Figure 136: Example of I2C Byte Write Bit Masking...167 Figure 137: Page Write Command...169 Figure 138: I2C Block Addressing ..170 Figure 139: Analog Temperature Sensor Structure Diagram...174 Figure 140: TS Output vs. Temperature, VDD = 3.3 V ...175
Datasheet Revision 2.1 13-Nov-2020
CFR0011-120-00 7 of 243 © 2020 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN-24L 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 Timing Characteristics 3.6 Oscillator Characteristics 3.6.1 OSC Power-On Delay 3.7 ACMP Characteristics 3.8 Internal Vref Characteristics 3.9 Output Buffers Characteristics 3.10 Analog Temperature Sensor Characteristics 3.11 Programmable Operational Amplifier Characteristics 3.12 100K Digital Rheostat Characteristics 3.13 Analog Switches Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-Up/Down during Power-Up 5.5 I2C Mode IO Structure 5.5.1 I2C Mode Structure (for SCL and SDA) 5.6 Matrix OE IO Structure 5.7 GPI Structure 5.7.1 GPI Structure (for I0) 5.8 IO Pins Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.1.2 Initial Polarity Operations 7.2 2-bit LUT or Programmable Pattern Generator 7.2.1 2-Bit LUT or PGen Macrocell Used as 2-Bit LUT 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.3.2 Initial Polarity Operations 7.4 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.4.1 4-Bit LUT Macrocell Used as 4-Bit LUT 7.5 3-Bit LUT or Pipe Delay/Ripple Counter Macrocell 7.5.1 3-Bit LUT or Pipe Delay Macrocells Used as 3-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 4-Bit LUT or DFF/Latch with 16-Bit Counter/Delay Macrocell 8.2.1 4-Bit LUT or DFF/LATCH with 16-Bit CNT/DLY Block Diagram 8.2.2 4-Bit LUT or 16-Bit Counter/Delay Macrocells Used as 4-Bit LUTs 8.3 CNT/DLY/FSM Timing Diagrams 8.3.1 Delay Mode CNT/DLY0 to CNT/DLY6 8.3.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY6 8.3.3 One-Shot Mode CNT/DLY0 to CNT/DLY6 8.3.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY6 8.3.5 Edge Detection Mode CNT/DLY1 to CNT/DLY6 8.3.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY6 8.3.7 CNT/FSM Mode CNT/DLY0 8.3.8 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.4 Wake and Sleep Controller 9 Analog Comparators 9.1 Analog Comparators Overview 9.1.1 ACMP0L Block Diagram 9.1.2 ACMP1L Block Diagram 9.2 Chopper Analog Comparator 9.3 ACMP Sampling Mode 9.4 ACMP Typical Performance 10 Programmable Operational Amplifiers 10.1 General Description 10.2 Modes of Operation 10.2.1 Operational Amplifier Mode 10.2.2 Instrumentation Amplifier Mode 10.2.3 Analog Comparator Mode 10.2.4 Voltage Regulator Mode 10.2.5 Current Sink Mode 10.3 Op Amp Typical Performance 11 Analog Switch Macrocell 11.1 Analog Switch General Description 11.2 Half Bridge Mode 12 Digital Rheostats and Programmable Trim Block 12.1 Potentiometer Mode 12.2 Calculating Actual Resistance 12.3 Digital Rheostat Value Self-programming into the NVM 12.4 Trimming process Using Programmable Trim Block 12.4.1 Trimming Process with Auto-Trim Option Enabled 12.4.2 I2C Controlled Trimming Process with Auto-Trim Option Enabled 12.4.3 Changing Rheostat Value Directly via I2C 12.5 Using Chopper ACMP 13 Programmable Delay/Edge Detector 13.1 Programmable Delay Timing Diagram - Edge Detector Output 14 Additional Logic Function. Deglitch Filter 15 Voltage Reference 15.1 Voltage Reference Overview 15.2 Vref Selection Table 15.3 Vref Block Diagram 16 Clocking 16.1 OSC General Description 16.2 Oscillator0 (2.048 kHz) 16.3 Oscillator1 (2.048 MHz) 16.4 Oscillator2 (25 MHz) 16.5 CNT/DLY Clock Scheme 16.6 External Clocking 16.6.1 IO1 Source for Oscillator0 (2.048 kHz) 16.6.2 IO3 Source for Oscillator1 (2.048 MHz) 16.6.3 IO2 Source for Oscillator2 (25 MHz) 16.7 Oscillators Power-On Delay 16.8 Oscillators Accuracy 17 Power-On Reset 17.1 General Operation 17.2 POR Sequence 17.3 Macrocells Output States During POR Sequence 17.3.1 Initialization 17.3.2 Power-Down 18 I2C Serial Communications Macrocell 18.1 I2C Serial Communications Macrocell Overview 18.2 I2C Serial Communications Device Addressing 18.3 I2C Serial General Timing 18.4 I2C Serial Communications Commands 18.4.1 Byte Write Command 18.4.2 Sequential Write Command 18.4.3 Current Address Read Command 18.4.4 Random Read Command 18.4.5 Sequential Read Command 18.4.6 I2C Serial Reset Command 18.5 Chip Configuration Data Protection 18.6 I2C Serial Command Register Map 18.7 I2C Additional Options 18.7.1 Reading Counter Data via I2C 18.7.2 I2C Byte Write Bit Masking 19 Non-Volatile Memory 19.1 Serial NVM Write Operations 19.2 Serial NVM Read Operations 19.3 Serial NVM Erase Operations 19.4 Acknowledge Polling 19.5 Low power standby mode 19.6 Emulated EEPROM Write Protection 20 Analog Temperature Sensor 21 Register Definitions 21.1 Register Map 22 Package Top Marking System Definition 22.1 STQFN-24L 3 mm x 3 mm x 0.55 mm, 0.4P FCD Package 23 Package Information 23.1 Package outlines FOR STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package 23.2 STQFN Handling 23.3 Soldering Information 24 Ordering Information 24.1 Tape and Reel Specifications 25 Layout Guidelines 25.1 STQFN 24L 3 mm x 3 mm x 0.55 mm 0.4P Green Package Glossary Revision History
