Datasheet SLG47004 (Dialog Semiconductor) - 10

SLG47004
GreenPAK Programmable Mixed-Signal Matrix
with In-System Programmability and Advanced Analog Features
1 Preliminary Block Diagram AGND OA1-OA1_OUT OA1+ IO6 IO7 Oscillators
1024 Position
Rheostat 2.048
MHz 2.048
kHz 25
MHz HD
Buffer 1024 Position
Rheostat
VDDA Multiple Time
Programmable
Memory In-System
Programmability Programmable
Trim Block 2K bits
EEPROM
Emulation IO5 Combination Function Macrocells
OA0+
Chopper
ACMP ACMP1L ACMP0L OA0Prog,
OA0 2-bit
LUT2_0
or DFF0 2-bit
LUT2_1
or DFF1 2-bit
LUT2_2
or DFF2 2-bit
LUT2_3
or PGen 3bit
LUT3_0
or DFF3 3-bit
LUT3_1
or DFF4 3-bit
LUT3_2
or DFF5 3-bit
LUT3_3
or DFF6 3-bit
LUT3_4
or DFF7 3-bit
LUT3_5
or DFF8 3-bit
LUT3_6
or DFF9 4-bit
LUT4_0
or DFF10 IO4 IO3 Int.
OA
OA0_OUT RH0_A IO2 3-bit LUT3_13
or Pipe Delay
or Ripple CNT Prog,
OA1 Low Power Vref Multi-Function Macrocells Temperature
Sensor Analog Switch 0/
Voltage Regulator Mode
RH0_B Analog Switch 1/
Current Sink Mode I2C Serial
Communication RH1_A RH1_B 3-bit LUT3_7
/DFF11
+8bit
CNT/DLY1 3-bit LUT3_8
/DFF12
+8bit
CNT/DLY2 3-bit LUT3_9
/DFF13
+8bit
CNT/DLY3 3-bit LUT3_11
/DFF15
+8bit
CNT/DLY5 3-bit LUT3_12
/DFF16
+8bit
CNT/DLY6 4-bit LUT4_1
/DFF17+
16bit
CNT/DLY0 Programmable
Delay or Edge
Detect SCL Filter with
Edge Detect SDA 3-bit LUT3_10
/DFF14
+8bit
CNT/DLY4 IO1 VDD POR IO0 GND Figure 1: Block Diagram Datasheet
CFR0011-120-00 Revision 2.1
10 of 243 13-Nov-2020
© 2020 Dialog Semiconductor