Datasheet LTC1694-1 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | SMBus/I2C Accelerator |
| Pages / Page | 8 / 7 — APPLICATIONS INFORMATION. Connecting Multiple LTC1694-1 in Parallel. ACK … |
| File Format / Size | PDF / 185 Kb |
| Document Language | English |
APPLICATIONS INFORMATION. Connecting Multiple LTC1694-1 in Parallel. ACK Data Setup Time
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LTC1694-1
U U W U APPLICATIONS INFORMATION
Using equations 4 and 5 to check exact value of tr: The LTC1694-1 2.2mA pull-up current is activated when t the SMBus host releases the SDA line, allowing the r = 0.535µs + 0.254µs = 0.79µs voltage to rise above the LTC1694-1’s comparator thresh- Using equation 7 to check tf: old of 0.65V. If an SMBus slave device has a high value t of R f = 0.222µs S, a longer time is required for this SMBus slave device to pull SDA low before the rising edge of the ACK which is less than 0.3µs. clock pulse. Using equation 1 to check VOL: To ensure sufficient data setup time for ACK, SMBus slave VOL = (3.3 • 700)/[700 + (27 • 103)] = 83mV devices with high values of RS, should pull the SDA low earlier. Typically, a minimum setup time of 1.5µs is needed which is less than 0.4V. for an SMBus device with an RS of 700Ω and a bus And using equation 2 to check the initial slew rate: capacitance of 200pF. SR = 3.3/[(27 • 103) • (200 • 10–12)] = 0.61V/µs An alternative is that the SMBus slave device can hold SCL which is greater than 0.5V/µs. line low until the SDA line reaches a stable state. Then, SCL can be released to generate the ACK clock pulse. Therefore, the value of RP chosen is 27k.
Connecting Multiple LTC1694-1 in Parallel ACK Data Setup Time
The LTC1694-1 is designed to guarantee a maximum Care must be taken in selecting the value of RS (in series SMBus rise time of 1µs with a bus capacitance of 200pF. with the pull-down driver) to ensure that the data setup In some cases where the bus capacitance is higher than time requirement for ACK (acknowledge) is fulfilled. An 200pF, multiple LTC1694-1s can be connected in parallel acknowledge is accomplished by the SMBus host releas- to provide a higher pull-up current to meet the rise time ing the SDA line (pulling high) at the end of the last bit sent requirement. Figure 3 shows a typical application with two and the SMBus slave device pulling the SDA line low LTC1694-1s connected in parallel to supply a pull-up before the rising edge of the ACK clock pulse. current of 4.4mA. VCC 5V 5 1 1 5 SMBus1 V V CC CC SMBus1 C1 LTC1694-1 LTC1694-1 0.1µF 4 2 2 4 SMBus2 GND GND SMBus2 R R P1 P2 SCL SMBus SDA CLK DATA CLK DATA IN IN IN IN CLK DATA CLK DATA OUT OUT OUT OUT DEVICE 1 DEVICE N 1694-1 f03
Figure 3. Paralleling Two LTC1694-1 to Provide 4.4mA of Pull-Up Current
16941fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7
U U W U APPLICATIONS INFORMATION
Using equations 4 and 5 to check exact value of tr: The LTC1694-1 2.2mA pull-up current is activated when t the SMBus host releases the SDA line, allowing the r = 0.535µs + 0.254µs = 0.79µs voltage to rise above the LTC1694-1’s comparator thresh- Using equation 7 to check tf: old of 0.65V. If an SMBus slave device has a high value t of R f = 0.222µs S, a longer time is required for this SMBus slave device to pull SDA low before the rising edge of the ACK which is less than 0.3µs. clock pulse. Using equation 1 to check VOL: To ensure sufficient data setup time for ACK, SMBus slave VOL = (3.3 • 700)/[700 + (27 • 103)] = 83mV devices with high values of RS, should pull the SDA low earlier. Typically, a minimum setup time of 1.5µs is needed which is less than 0.4V. for an SMBus device with an RS of 700Ω and a bus And using equation 2 to check the initial slew rate: capacitance of 200pF. SR = 3.3/[(27 • 103) • (200 • 10–12)] = 0.61V/µs An alternative is that the SMBus slave device can hold SCL which is greater than 0.5V/µs. line low until the SDA line reaches a stable state. Then, SCL can be released to generate the ACK clock pulse. Therefore, the value of RP chosen is 27k.
Connecting Multiple LTC1694-1 in Parallel ACK Data Setup Time
The LTC1694-1 is designed to guarantee a maximum Care must be taken in selecting the value of RS (in series SMBus rise time of 1µs with a bus capacitance of 200pF. with the pull-down driver) to ensure that the data setup In some cases where the bus capacitance is higher than time requirement for ACK (acknowledge) is fulfilled. An 200pF, multiple LTC1694-1s can be connected in parallel acknowledge is accomplished by the SMBus host releas- to provide a higher pull-up current to meet the rise time ing the SDA line (pulling high) at the end of the last bit sent requirement. Figure 3 shows a typical application with two and the SMBus slave device pulling the SDA line low LTC1694-1s connected in parallel to supply a pull-up before the rising edge of the ACK clock pulse. current of 4.4mA. VCC 5V 5 1 1 5 SMBus1 V V CC CC SMBus1 C1 LTC1694-1 LTC1694-1 0.1µF 4 2 2 4 SMBus2 GND GND SMBus2 R R P1 P2 SCL SMBus SDA CLK DATA CLK DATA IN IN IN IN CLK DATA CLK DATA OUT OUT OUT OUT DEVICE 1 DEVICE N 1694-1 f03
Figure 3. Paralleling Two LTC1694-1 to Provide 4.4mA of Pull-Up Current
16941fa Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights. 7
