Datasheet ADCA3952 (Analog Devices) - 10
| Manufacturer | Analog Devices |
| Description | DOCSIS 3.1, Power Doubler Hybrid Module, 45 MHz to 1218 MHz |
| Pages / Page | 12 / 10 — ADCA3952. Data Sheet. APPLICATIONS INFORMATION. 500. 450. (mA). 400. NT … |
| File Format / Size | PDF / 336 Kb |
| Document Language | English |
ADCA3952. Data Sheet. APPLICATIONS INFORMATION. 500. 450. (mA). 400. NT 400. RRE U. (mA. 350. N 300. LY P P U. URRE. 300. LY 200. P P U S. 250. 100. 10k. 100k
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ADCA3952 Data Sheet APPLICATIONS INFORMATION
Basic connections for operating the ADCA3952 are shown in In systems that require the bias current to be lower than the Figure 14. Both the INPUT pin (Pin 1) and the OUTPUT pin default but it is not critical, a resistor can be placed between the (Pin 9) of the ADCA3952 are matched to 75 Ω. The VCC pin IADJ pin (Pin 4 ) and ground to set the current (see Figure 15). (Pin 5) requires 24 V for typical operation. It is recommended Figure 13 illustrates the typical supply current of the ADCA3952 to leave the IADJ pin (Pin 4) open for full bias operation. For in this configuration for a range of resistor values between 100 Ω bias control on the ADCA3952 supply current, apply an external and 40 kΩ. control voltage between −0.6 V and +1 V at the IADJ pin.
500
Figure 12 illustrates the typical supply current over the control voltages at the IADJ pin of the ADCA3992.
500 450 (mA) 400 NT 400 ) RRE U (mA C T 350 N 300 LY P P U URRE S C 300 LY 200 P P U S 250 100 100 1k 10k 100k
-015
RIADJ RESISTOR VALUE (Ω)
25050
0
Figure 13. Supply Current vs. RIADJ Resistor Value
–0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
012
V
050-
IADJ (V)
25 Figure 12. Supply Current vs. VIADJ at the IADJ Pin
ADCA3952 INPUT 1 75Ω LINE OUTPUT 9 75Ω LINE BIAS 2 3 4 5 7 8 IADJ VCC GND GND +24V TYPICAL
3 01
NO CONNECT FOR FULL BIAS
50-
–0.6V TO 1V FOR ADJUSTABLE BIAS
250 Figure 14. Basic Connections
ADCA3952 INPUT 1 75Ω LINE OUTPUT 9 75Ω LINE BIAS 2 3 4 5 7 8 IADJ VCC GND R GND IADJ +24V TYPICAL
014 5050- 2 Figure 15. IADJ Bias Control Connections Rev. 0 | Page 10 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL PERFORMANCE DISTORTION DATA (40 MHz TO 550 MHz), ERROR RATES, AND TOTAL COMPOSITE POWER ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS S-PARAMETERS 9 dB TILT PERFORMANCE THEORY OF OPERATION APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
ADCA3952 Data Sheet APPLICATIONS INFORMATION
Basic connections for operating the ADCA3952 are shown in In systems that require the bias current to be lower than the Figure 14. Both the INPUT pin (Pin 1) and the OUTPUT pin default but it is not critical, a resistor can be placed between the (Pin 9) of the ADCA3952 are matched to 75 Ω. The VCC pin IADJ pin (Pin 4 ) and ground to set the current (see Figure 15). (Pin 5) requires 24 V for typical operation. It is recommended Figure 13 illustrates the typical supply current of the ADCA3952 to leave the IADJ pin (Pin 4) open for full bias operation. For in this configuration for a range of resistor values between 100 Ω bias control on the ADCA3952 supply current, apply an external and 40 kΩ. control voltage between −0.6 V and +1 V at the IADJ pin.
500
Figure 12 illustrates the typical supply current over the control voltages at the IADJ pin of the ADCA3992.
500 450 (mA) 400 NT 400 ) RRE U (mA C T 350 N 300 LY P P U URRE S C 300 LY 200 P P U S 250 100 100 1k 10k 100k
-015
RIADJ RESISTOR VALUE (Ω)
25050
0
Figure 13. Supply Current vs. RIADJ Resistor Value
–0.6 –0.4 –0.2 0 0.2 0.4 0.6 0.8 1.0
012
V
050-
IADJ (V)
25 Figure 12. Supply Current vs. VIADJ at the IADJ Pin
ADCA3952 INPUT 1 75Ω LINE OUTPUT 9 75Ω LINE BIAS 2 3 4 5 7 8 IADJ VCC GND GND +24V TYPICAL
3 01
NO CONNECT FOR FULL BIAS
50-
–0.6V TO 1V FOR ADJUSTABLE BIAS
250 Figure 14. Basic Connections
ADCA3952 INPUT 1 75Ω LINE OUTPUT 9 75Ω LINE BIAS 2 3 4 5 7 8 IADJ VCC GND R GND IADJ +24V TYPICAL
014 5050- 2 Figure 15. IADJ Bias Control Connections Rev. 0 | Page 10 of 12 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS GENERAL PERFORMANCE DISTORTION DATA (40 MHz TO 550 MHz), ERROR RATES, AND TOTAL COMPOSITE POWER ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS S-PARAMETERS 9 dB TILT PERFORMANCE THEORY OF OPERATION APPLICATIONS INFORMATION OUTLINE DIMENSIONS ORDERING GUIDE
