Data SheetADPA7002CHIPTYPICAL PERFORMANCE CHARACTERISTICS Where IDQ = IDD (drain current) = RF signal applied to IDQ. 2020181516B)10d ( S14S5O+85°C +25°CS1112B)0–55°CS21dURN L TS22N ( 10–5AI, REG8B) d–106N ( AI–15G4–202–25014 16 18 20 22 24 28 30 32 34 36 38 40 42 44 46 48 010 20222426283032343638404244 013 FREQUENCY (GHz)FREQUENCY (GHz) 17236- 17236- Figure 10. Gain and Return Loss vs. Frequency Figure 13. Gain vs. Frequency for Various Temperatures 20204.0V600mA5.0V700mA1818800mA1616B)14B)14ddN (N (AIAI12G12G10108866 1 1 0 014 2022242628303234363840424420222426283032343638404244FREQUENCY (GHz)FREQUENCY (GHz) 17236- 17236- Figure 11. Gain vs. Frequency for Various Drain Voltages Figure 14. Gain vs. Frequency for Various Quiescent Drain Currents 00+85°C–5+25°C–55.0V–55°C4.0VB)B)dd((SSSSO–10O–10URN LURN LTT–15–15REREUTUTINPINP–20–20–25–2520222426283032343638404244 012 20222426283032343638404244 015 FREQUENCY (GHz) 17236- FREQUENCY (GHz) 17236- Figure 12. Input Return Loss vs. Frequency for Various Temperatures, Figure 15. Input Return Loss vs. Frequency for Various Drain Voltages VDD = 5 V, IDQ = 600 mA Rev. C | Page 7 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS 20 GHz TO 34 GHz FREQUENCY RANGE 34 GHz TO 44 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS CONSTANT DRAIN CURRENT (IDD) OPERATION THEORY OF OPERATION ADPA7002CHIP ASSEMBLY AND CIRCUIT DIAGRAMS ALTERNATE ASSEMBLY DIAGRAM BIASING PROCEDURES BIASING THE ADPA7002CHIP WITH THE HMC980LP4E Application Circuit Setup Limiting VGATE to Meet ADPA7002CHIP VGGx AMR Requirement HMC980LP4E Bias Sequence Constant Drain Current Bias vs. Constant Gate Voltage Bias MOUNTING AND BONDING TECHNIQUES FOR MILLIMETER WAVE GAAS MMICS Handling Precautions Mounting Wire Bonding OUTLINE DIMENSIONS ORDERING GUIDE