Datasheet HMC8415LP6GE (Analog Devices) - 7

Data Sheet HMC8415LP6GE INTERFACE SCHEMATICS GND
006 003
RFOUT
16688- 16688- Figure 3. GND Interface Schematic Figure 6. RFOUT Interface Schematic 004
VDD1A/VDD1B/VDD2A/VDD2B/VDD3A/VDD3B RFIN
16688- 007 16688- Figure 4. RFIN Interface Schematic Figure 7. VDD1A, VDD1B, VDD2A, VDD2B, VDD3A, and VDD3B Interface Schematic 005
VGG1A/VGG1B/VGG2A/VGG2B/VGG3A/VGG3B
16688- Figure 5. VGG1A, VGG1B, VGG2A, VGG2B, VGG3A, and VGG3B Interface Schematic Rev. A | Page 7 of 23 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS TOTAL TARGET QUIESCENT CURRENT BY VDDxA/VDDxB ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION TYPICAL APPLICATION CIRCUIT AND PULSOR CIRCUIT USING THE EV1HMC8415LP6G WITH THE DRAIN BIAS PULS0R BOARD RECOMMENDED BIAS SEQUENCE Power-Up Bias Concept for the EV1HMC8415LP6G with the Pulsor Power-Down Bias Concept for the EV1HMC8415LP6G with the Pulsor MAKING AVERAGE TO PULSED APPROXIMATIONS EVALUATION PCB BILL OF MATERIALS OUTLINE DIMENSIONS ORDERING GUIDE