Datasheet HMC1144 (Analog Devices) - 6
| Manufacturer | Analog Devices |
| Description | 35 GHz to 70 GHz, GaAs, pHEMT, MMIC, Medium Power Amplifier |
| Pages / Page | 16 / 6 — HMC1144. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VGG1A. … |
| Revision | D |
| File Format / Size | PDF / 351 Kb |
| Document Language | English |
HMC1144. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VGG1A. VDD1A VDD2A. VDD3A. VDD4A. RFOUT. TOP VIEW. (Not to Scale). RFIN
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HMC1144 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGG1A VDD1A VDD2A VDD3A VDD4A 2 3 4 5 6 7 RFOUT HMC1144 TOP VIEW (Not to Scale) RFIN 1 12 11 10 9 8
-002
VGG1B VDD1B VDD2B VDD3B VDD4B
13143 Figure 2. Pad Configuration
Table 5. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2 VGG1A Gate Control Pad for Alternate Bias Configuration. See Figure 4 for the interface schematic.. 3 to 6 VDD1A to VDD4A Drain Bias Voltage Pads for the Amplifier. External bypass capacitors of 100 pF and 0.1 μF are required. See Figure 5 for the interface schematic. 7 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 8 to 11 VDD4B to VDD1B Drain Bias Voltage Pads for Alternate Bias Configuration. External bypass capacitors of 100 pF and 0.1 μF are required for decoupling. See Figure 7 for the interface schematic. 12 VGG1B Gate Control Pad for the Amplifier. External bypass capacitors of 100 pF and 0.1 μF are required. See Figure 8 for the interface schematic. Die Bottom GND Die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
INTERFACE SCHEMATICS
3
V
00
DD1B TO VDD4B RFIN
32 1 143- 3- 13 14 13 Figure 3. RFIN Interface Schematic Figure 7. VDD1B to VDD4B Interface Schematic 4 -00
VGG1A V
108
GG1B
3143 43- 1 131 Figure 4. VGG1A Interface Schematic Figure 8. VGG1B Interface Schematic
VDD1A TO VDD4A
5 7
GND
00 00 3- 3- 14 14 13 13 Figure 5. VDD1A to VDD4A Interface Schematic Figure 9. GND Interface Schematic 6 00
RFOUT
143- 13 Figure 6. RFOUT Interface Schematic Rev. D | Page 6 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL SPECIFICATIONS 35 GHz TO 40 GHz FREQUENCY RANGE 40 GHz TO 50 GHz FREQUENCY RANGE 50 GHz TO 70 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ALTERNATE BIASING CONFIGURATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE
HMC1144 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VGG1A VDD1A VDD2A VDD3A VDD4A 2 3 4 5 6 7 RFOUT HMC1144 TOP VIEW (Not to Scale) RFIN 1 12 11 10 9 8
-002
VGG1B VDD1B VDD2B VDD3B VDD4B
13143 Figure 2. Pad Configuration
Table 5. Pad Function Descriptions Pad No. Mnemonic Description
1 RFIN RF Input. This pad is ac-coupled and matched to 50 Ω. See Figure 3 for the interface schematic. 2 VGG1A Gate Control Pad for Alternate Bias Configuration. See Figure 4 for the interface schematic.. 3 to 6 VDD1A to VDD4A Drain Bias Voltage Pads for the Amplifier. External bypass capacitors of 100 pF and 0.1 μF are required. See Figure 5 for the interface schematic. 7 RFOUT RF Output. This pad is ac-coupled and matched to 50 Ω. See Figure 6 for the interface schematic. 8 to 11 VDD4B to VDD1B Drain Bias Voltage Pads for Alternate Bias Configuration. External bypass capacitors of 100 pF and 0.1 μF are required for decoupling. See Figure 7 for the interface schematic. 12 VGG1B Gate Control Pad for the Amplifier. External bypass capacitors of 100 pF and 0.1 μF are required. See Figure 8 for the interface schematic. Die Bottom GND Die bottom must be connected to RF/dc ground. See Figure 9 for the interface schematic.
INTERFACE SCHEMATICS
3
V
00
DD1B TO VDD4B RFIN
32 1 143- 3- 13 14 13 Figure 3. RFIN Interface Schematic Figure 7. VDD1B to VDD4B Interface Schematic 4 -00
VGG1A V
108
GG1B
3143 43- 1 131 Figure 4. VGG1A Interface Schematic Figure 8. VGG1B Interface Schematic
VDD1A TO VDD4A
5 7
GND
00 00 3- 3- 14 14 13 13 Figure 5. VDD1A to VDD4A Interface Schematic Figure 9. GND Interface Schematic 6 00
RFOUT
143- 13 Figure 6. RFOUT Interface Schematic Rev. D | Page 6 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY ELECTRICAL SPECIFICATIONS 35 GHz TO 40 GHz FREQUENCY RANGE 40 GHz TO 50 GHz FREQUENCY RANGE 50 GHz TO 70 GHz FREQUENCY RANGE ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION ALTERNATE BIASING CONFIGURATION MOUNTING AND BONDING TECHNIQUES FOR MILLIMETERWAVE GaAs MMICS Handling Precautions Mounting Wire Bonding TYPICAL APPLICATION CIRCUIT ASSEMBLY DIAGRAM OUTLINE DIMENSIONS ORDERING GUIDE
