Datasheet ADRF5545A (Analog Devices) - 7

Data Sheet ADRF5545A INTERFACE SCHEMATICS PD-CHAB BP-CHA, BP-CHB CLAMP GND
003 107 20051-
GND GND
20051- Figure 3. GND Interface Figure 6. PD-CHAB, BP-CHx Interface
SWVDD-CHAB CLAMP VDD GND GND RXOUT-CHA, RXOUT-CHB SWCTRL-CHAB
105 108
GND
20051- 20051- Figure 4. RXOUT-CHx Interface Figure 7. SWCTRL-CHAB, SWVDD-CHAB Interface
VDD1-CHx, VDD2-CHx CLAMP
106
GND GND
20051- Figure 5. VDD1-CHx, VDD2-CHx Interface Rev. B | Page 7 of 20 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS 2.6 GHZ TUNED OPERATION ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS INTERFACE SCHEMATICS TYPICAL PERFORMANCE CHARACTERISTICS RECEIVE OPERATION, HIGH GAIN MODE RECEIVE OPERATION, LOW GAIN MODE TRANSMIT OPERATION RECEIVE OPERATION, HIGH GAIN MODE WITH 2.6 GHZ TUNING RECEIVE OPERATION, LOW GAIN MODE WITH 2.6 GHz TUNING TRANSMIT OPERATION AT WITH 2.6 GHz TUNING THEORY OF OPERATION SIGNAL PATH SELECT Transmit Operation Receive Operation BIASING SEQUENCE APPLICATIONS INFORMATION 2.6 GHZ OPERATION OUTLINE DIMENSIONS ORDERING GUIDE