Datasheet AD8324 (Analog Devices)

3.3 V, Upstream, Cable Line Driver Data Sheet AD8324 FEATURES FUNCTIONAL BLOCK DIAGRAM BYP Supports DOCSIS 2.0 and EuroDOCSIS specifications for reverse path transmission systems V V Gain programmable in 1 dB steps over a 59 dB range IN+ OUT+ DIFF Low distortion at 61 dBmV output OR SINGLE VERNIER ATTENUATION OUTPUT INPUT CORE STAGE −59 dBc SFDR at 21 MHz AMP VIN– VOUT– −54 dBc SFDR at 65 MHz Z Z OUT DIFF = IN (SINGLE) = 550Ω 8 75Ω Output noise level at minimum gain 1.3 nV/√Hz ZIN (DIFF) = 1100Ω DECODE Maintains 75 Ω output impedance in transmit-enable and POWER- transmit-disable condition 8 RAMP DOWN LOGIC Upper bandwidth of 100 MHz (full gain range) AD8324 DATA LATCH 3.3 V supply operation 8 Supports SPI® interfaces SHIFT
01
REGISTER
-0 0 9-
APPLICATIONS
433 0
GND DATEN SDATA CLK TXEN SLEEP DOCSIS 2.0 and EuroDOCSIS cable modems
Figure 1.
CATV set-top boxes CATV telephony modems Coaxial and twisted pair line drivers GENERAL DESCRIPTION
The AD8324 is a low cost amplifier designed for coaxial line
–40
driving. The features and specifications make the AD8324 ideally suited for DOCSIS® 2.0 and EuroDOCSIS applications. The gain of the AD8324 is digitally controlled. An 8-bit serial
–50 VOUT = 61dBmV @ DEC 60 THIRD HARMONIC
word determines the desired output gain over a 59 dB range,
Bc)
resulting in gain changes of 1 dB/LSB.
d –60
The AD8324 accepts a differential or single-ended input signal. The output is specified for driving a 75 Ω load through a 1:1 transformer.
DISTORTION ( VOUT = 61dBmV @ DEC 60 –70 SECOND HARMONIC
Distortion performance of –54 dBc is achieved with an output level up to 61 dBmV at 65 MHz bandwidth.
–80
04339-0-002 This device has a sleep mode function that reduces the quiescent
5 15 25 35 45 55 65
current to 30 μA and a full power-down function that reduces
FREQUENCY (MHz)
power-down current to 2.5 mA. Figure 2. Worst Harmonic Distortion vs. Frequency The AD8324 is packaged in a low cost, 20-lead LFCSP and a 20-lead QSOP. The AD8324 operates from a single 3.3 V supply.
Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2003–2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS LOGIC INPUTS (TTL-/CMOS-COMPATIBLE LOGIC) TIMING REQUIREMENTS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TEST CIRCUIT APPLICATIONS INFORMATION GENERAL APPLICATIONS CIRCUIT DESCRIPTION GAIN PROGRAMMING FOR THE AD8324 INPUT BIAS, IMPEDANCE, AND TERMINATION OUTPUT BIAS, IMPEDANCE, AND TERMINATION POWER SUPPLY SIGNAL INTEGRITY LAYOUT CONSIDERATIONS INITIAL POWER-UP RAMP PIN AND BYP PIN FEATURES POWER SAVING FEATURES DISTORTION, ADJACENT CHANNEL POWER, AND DOCSIS UTILIZING DIPLEX FILTERS NOISE AND DOCSIS DIFFERENTIAL SIGNAL SOURCE DIFFERENTIAL SIGNAL FROM SINGLE-ENDED SOURCE SINGLE-ENDED SOURCE OUTLINE DIMENSIONS ORDERING GUIDE