Datasheet AD5560 (Analog Devices) - 9
| Manufacturer | Analog Devices |
| Description | 1.2 A Programmable Device Power Supply with Integrated 16-Bit Level Setting DACs |
| Pages / Page | 66 / 9 — Data Sheet. AD5560. Parameter. Min. Typ. Max. Unit. Test … |
| Revision | E |
| File Format / Size | PDF / 2.1 Mb |
| Document Language | English |
Data Sheet. AD5560. Parameter. Min. Typ. Max. Unit. Test Conditions/Comments
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Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments
SETTLING TIME (FV, MEASURE Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value CURRENT) 380 nF, ESR 74 to 140 mΩ) MI (1200 mA EXTFORCE1 Range)1 30 40 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load MI (900 mA EXTFORCE1 Range)1 32 42 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load MI (500 mA EXTFORCE2 Range)1 69 95 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load MI (300 mA EXTFORCE2 Range)1 70 100 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load MI (25 mA Range)1, 3 650 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load MI (2.5 mA Range)1, 3 6400 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load MI Buffer Alone1 10 15 µs 0.5 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV, MEASURE Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value VOLTAGE) 380 nF, ESR 74 to 140 mΩ) MV (1200 mA Range)1 16 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load MV (900 mA Range)1 20 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load MV (500 mA Range)1 34 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load MV (300 mA Range)1 25 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load MV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load MV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load MV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load MV Buffer Alone1 2 5 µs 10 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV) SAFE MODE To within 100 mV of programmed value FV (1200 mA EXTFORCE1 Range1 25 µs 3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load FV (180 mA EXTFORCE1 Range)1 303 µs 3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 μF, full dc load FV (100 mA EXTFORCE2 Range)1 660 µs 8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 μF, full dc load FV (25 mA Range)1, 3 760 1000 µs 20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load SWITCHING TRANSIENTS Range Change Transient1 0.5 % of FV CDUT = 10 μF, changing from higher to adjacent lower ranges (except EXTFORCE1 to EXTFORCE2) 20 mV CDUT = 10 μF, changing from lower (5 µA) to higher range (EXTFORCE1) 0.5 % of FV CDUT = 100 μF, changing between all ranges DAC SPECIFICATIONS Force/Comparator/Offset DACs Resolution 16 Bits Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic Offset DAC Gain Error −20 +20 mV Clamp DAC CLL < CLH Resolution 16 Bits Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic OSD DAC Resolution 16 Bits Voltage Output Span 0.62 5 V VREF = 5 V Differential Nonlinearity1 −2 +2 LSB DGS DAC Resolution 16 Bits Voltage Output Span 0 5 V VREF = 5 V Differential Nonlinearity1 −2 +2 LSB Comparator DAC Dynamic Output Voltage Settling Time1 3.5 6 µs 1 V change to 1 LSB Slew Rate1 1 V/µs Digital-to-Analog Glitch 10 nV-s Energy1 Glitch Impulse Peak Amplitude1 40 mV Rev. E | Page 9 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE
Data Sheet AD5560 Parameter Min Typ Max Unit Test Conditions/Comments
SETTLING TIME (FV, MEASURE Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value CURRENT) 380 nF, ESR 74 to 140 mΩ) MI (1200 mA EXTFORCE1 Range)1 30 40 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load MI (900 mA EXTFORCE1 Range)1 32 42 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load MI (500 mA EXTFORCE2 Range)1 69 95 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load MI (300 mA EXTFORCE2 Range)1 70 100 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load MI (25 mA Range)1, 3 650 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load MI (2.5 mA Range)1, 3 6400 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load MI Buffer Alone1 10 15 µs 0.5 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV, MEASURE Compensation Register 1 = 0x4880 (229 nF to To within 10 mV of programmed value VOLTAGE) 380 nF, ESR 74 to 140 mΩ) MV (1200 mA Range)1 16 µs 3.7 V step, RDUT = 2.4 Ω, CDUT = 0.22 µF, full dc load MV (900 mA Range)1 20 µs 8 V step, RDUT = 8.8 Ω, CDUT = 0.22 µF, full dc load MV (500 mA Range)1 34 µs 15 V step, RDUT = 30 Ω, CDUT = 0.22 µF, full dc load MV (300 mA Range)1 25 µs 10 V step, RDUT = 33.3 Ω, CDUT = 0.22 µF, full dc load MV (25 mA Range)1, 3 125 180 µs 20 V step, RDUT = 800 Ω, CDUT = 0.22 µF, full dc load MV (2.5 mA Range)1, 3 300 500 µs 10 V step, RDUT = 4 kΩ, CDUT = 0.22 µF, full dc load MV (250 µA Range)1, 3 300 500 µs 10 V step, RDUT = 40 kΩ, CDUT = 0.22 µF, full dc load MV Buffer Alone1 2 5 µs 10 V step using MEASOUT high-Z to within 10 mV of final value SETTLING TIME (FV) SAFE MODE To within 100 mV of programmed value FV (1200 mA EXTFORCE1 Range1 25 µs 3.7 V step, RDUT = 3.1 Ω, CDUT = 0.22 µF, full dc load FV (180 mA EXTFORCE1 Range)1 303 µs 3 V step, RDUT = 16 Ω, CDUT = 0. 22 µF to 20 μF, full dc load FV (100 mA EXTFORCE2 Range)1 660 µs 8 V step, RDUT = 33.3 Ω, CDUT = 0. 22 µF to 20 μF, full dc load FV (25 mA Range)1, 3 760 1000 µs 20 V step, RDUT = 400 Ω, CDUT = 0.22 µF, full dc load SWITCHING TRANSIENTS Range Change Transient1 0.5 % of FV CDUT = 10 μF, changing from higher to adjacent lower ranges (except EXTFORCE1 to EXTFORCE2) 20 mV CDUT = 10 μF, changing from lower (5 µA) to higher range (EXTFORCE1) 0.5 % of FV CDUT = 100 μF, changing between all ranges DAC SPECIFICATIONS Force/Comparator/Offset DACs Resolution 16 Bits Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic Offset DAC Gain Error −20 +20 mV Clamp DAC CLL < CLH Resolution 16 Bits Voltage Output Span −22 +25 V VREF = 5 V, minimum and maximum values set by offset DAC Differential Nonlinearity1 −1 +1 LSB Guaranteed monotonic OSD DAC Resolution 16 Bits Voltage Output Span 0.62 5 V VREF = 5 V Differential Nonlinearity1 −2 +2 LSB DGS DAC Resolution 16 Bits Voltage Output Span 0 5 V VREF = 5 V Differential Nonlinearity1 −2 +2 LSB Comparator DAC Dynamic Output Voltage Settling Time1 3.5 6 µs 1 V change to 1 LSB Slew Rate1 1 V/µs Digital-to-Analog Glitch 10 nV-s Energy1 Glitch Impulse Peak Amplitude1 40 mV Rev. E | Page 9 of 66 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TERMINOLOGY THEORY OF OPERATION FORCE AMPLIFIER HW_INH Function DAC REFERENCE VOLTAGE (VREF) OPEN-SENSE DETECT (OSD) ALARM AND CLAMP DEVICE UNDER TEST GROUND (DUTGND) DUTGND Kelvin Sense Kelvin Alarm (KELALM) GPO COMPARATORS CURRENT CLAMPS Clamp Alarm Function (CLALM) Clamp Enable Function (CLEN/LOAD) SHORT-CIRCUIT PROTECTION GUARD AMPLIFIER COMPENSATION CAPACITORS CURRENT RANGE SELECTION HIGH CURRENT RANGES Master and Slaves in Force Voltage (FV) Mode Master in FV Mode, Slaves in Force Current (FI) Mode IDEAL SEQUENCE FOR GANG MODE COMPENSATION FOR GANG MODE SYSTEM FORCE/SENSE SWITCHES DIE TEMPERATURE SENSOR AND THERMAL SHUTDOWN MEASURE OUTPUT (MEASOUT) VMID VOLTAGE FORCE AMPLIFIER STABILITY Safe Mode Autocompensation Mode Manual Compensation Mode POLES AND ZEROS IN A TYPICAL SYSTEM MINIMIZING THE NUMBER OF EXTERNAL COMPENSATION COMPONENTS CFx Pins CCx Pins EXTRA POLES AND ZEROS IN THE AD5560 The Effect of CCx The Effect of CFx The Effect of RZ The Effect of RP COMPENSATION STRATEGIES Ensuring Stability into an Unknown Capacitor Up to a Maximum Value OPTIMIZING PERFORMANCE FOR A KNOWN CAPACITOR USING AUTOCOMPENSATION MODE ADJUSTING THE AUTOCOMPENSATION MODE DEALING WITH PARALLEL LOAD CAPACITORS DAC LEVELS FORCE AND COMPARATOR DACS CLAMP DACS OSD DAC DUTGND DAC OFFSET DAC OFFSET AND GAIN REGISTERS Offset and Gain Registers for the Force Amplifier DAC Offset and Gain Registers for the Comparator DACs Offset and Gain Registers for the Clamp DACs REFERENCE SELECTION CALIBRATION Reducing Zero-Scale Error Reducing Gain Error Calibration Example ADDITIONAL CALIBRATION SYSTEM LEVEL CALIBRATION CHOOSING AVDD/AVSS POWER SUPPLY RAILS CHOOSING HCAVSSx AND HCAVDDx SUPPLY RAILS POWER DISSIPATION PACKAGE COMPOSITION AND MAXIMUM VERTICAL FORCE SLEW RATE CONTROL Programmable Slew Rate Ramp Function SERIAL INTERFACE SPI INTERFACE SPI WRITE MODE SDO OUTPUT FUNCTION BUSY FUNCTION LOAD FUNCTION REGISTER UPDATE RATES CONTROL REGISTERS DPS AND DAC ADDRESSING READBACK MODE DAC READBACK POWER-ON DEFAULT USING THE HCAVDDx AND HCAVSSx SUPPLIES POWER SUPPLY SEQUENCING REQUIRED EXTERNAL COMPONENTS POWER SUPPLY DECOUPLING APPLICATIONS INFORMATION THERMAL CONSIDERATIONS TEMPERATURE CONTOUR MAP ON THE TOP OF THE PACKAGE TQFP_EP Package BGA Package OUTLINE DIMENSIONS ORDERING GUIDE
