Datasheet AD5751 (Analog Devices) - 10

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AD5751 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS P M T LT EC U TE A LT/ /IF SEL U C ESET W C C N FA R H NC NC N N 32 31 30 29 28 27 26 25 SDO/VFAULT 1 24 VSENSE+ CLRSEL 2 23 VOUT CLEAR 3 AD5751 22 GND DVCC 4 21 GND TOP VIEW GND 5 (Not to Scale) 20 COMP1 SYNC/RSET 6 19 COMP2 SCLK/OUTEN 7 18 IOUT SDIN/R0 8 17 AVDD 9 10 11 12 13 14 15 16 2 1 N D /R1 /R2 /R3 EF VI EXT EXT VR GN AD2 AD1 AD0 R R NOTES
-005
1. NC = NO CONNECT. CAN BE TIED TO GND. 2. THE EXPOSED PADDLE IS TIED TO GND.
7269 0 Figure 4. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 SDO/VFAULT Serial Data Output (SDO). In software mode, this pin is used to clock data from the input shift register in readback mode. Data is clocked out on the rising edge of SCLK and is valid on the falling edge of SCLK. This pin is a CMOS output. Short-Circuit Fault Alert (VFAULT). In hardware mode, this pin acts as a short-circuit fault alert pin and is asserted low when a short-circuit error is detected. This pin is an open-drain output and must be connected to a pull-up resistor. 2 CLRSEL In hardware or software mode, this pin selects the clear value, either zero-scale or midscale code. In software mode, this pin is implemented as a logic OR with the internal CLRSEL bit. 3 CLEAR Active High Input. Asserting this pin sets the output current/voltage to zero-scale code or midscale code of range selected (user-selectable). CLEAR is a logic OR with the internal clear bit. See the Asynchronous Clear (CLEAR) section for more details. In software mode, during power-up, the CLEAR pin level determines the power-on condition of the voltage channel, which can be active 0 V or tristate. 4 DVCC Digital Power Supply. 5 GND Ground Connection. 6 SYNC/RSET Positive Edge-Sensitive Latch (SYNC). In software mode, a rising edge parallel loads the input shift register data into the AD5751, also updating the output. Resistor Select (RSET). In hardware mode, this pin selects whether the internal or the external current sense resistor is used. If RSET = 0, the external sense resistor is chosen. If RSET = 1, the internal sense resistor is chosen. 7 SCLK/OUTEN Serial Clock Input (SCLK). In software mode, data is clocked into the input shift register on the falling edge of SCLK. This pin operates at clock speeds up to 50 MHz. Output Enable (OUTEN). In hardware mode, this pin acts as an output enable pin. 8 SDIN/R0 Serial Data Input (SDIN). In software mode, data must be valid on the falling edge of SCLK. Range Decode Bit (R0). In hardware mode, this pin, in conjunction with R1, R2, and R3, selects the output current/voltage range setting on the part. 9 AD2/R1 Device Addressing Bit (AD2). In software mode, this pin, in conjunction with AD0 and AD1, allows up to eight devices to be addressed on one bus. Range Decode Bit (R1). In hardware mode, this pin, in conjunction with R0, R2, and R3, selects the output current/voltage range setting on the part. Rev. E | Page 10 of 32 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Timing Characteristics Timing Diagrams Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Current Output Terminology Theory of Operation Software Mode Currrent Output Architecture Driving Inductive Loads Voltage Output Amplifier Driving Large Capacitive Loads Power-On State of the AD5751 Default Registers at Power-On Reset Function OUTEN Software Control Input Shift Register Readback Operation Hardware Control Transfer Function Detailed Description of Features Output Fault Alert—Software Mode Output Fault Alert—Hardware Mode Voltage Output Short-Circuit Protection Asynchronous Clear (CLEAR) External Current Setting Resistor Programmable Overrange Modes Packet Error Checking Applications Information Transient Voltage Protection Thermal Considerations Layout Guidelines Galvanically Isolated Interface Microprocessor Interfacing Outline Dimensions Ordering Guide