Datasheet ADP5014 (Analog Devices) - 7
| Manufacturer | Analog Devices |
| Description | Integrated Power Solution with Quad Low Noise Buck Regulators |
| Pages / Page | 34 / 7 — Data Sheet. ADP5014. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. … |
| Revision | A |
| File Format / Size | PDF / 840 Kb |
| Document Language | English |
Data Sheet. ADP5014. ABSOLUTE MAXIMUM RATINGS Table 3. Parameter. Rating. THERMAL RESISTANCE. Table 4. Thermal Resistance
Model Line for this Datasheet
Text Version of Document
Data Sheet ADP5014 ABSOLUTE MAXIMUM RATINGS Table 3.
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a AVIN to Ground −0.3 V to +6.5 V stress rating only; functional operation of the product at these PVIN1 to PGND1 −0.3 V to +6.5 V or any other conditions above those indicated in the operational PVIN2 to PGND2 −0.3 V to +6.5 V section of this specification is not implied. Operation beyond PVIN3 to PGND3 −0.3 V to +6.5 V the maximum operating conditions for extended periods may PVIN4 to PGND4 −0.3 V to +6.5 V affect product reliability. SW1 to PGND1 −0.3 V to +6.5 V
THERMAL RESISTANCE
SW2 to PGND2 −0.3 V to +6.5 V Thermal performance is directly linked to printed circuit board SW3 to PGND3 −0.3 V to +6.5 V (PCB) design and operating environment. Close attention to SW4 to PGND4 −0.3 V to +6.5 V PCB thermal design is required. PGND to Ground −0.3 V to + 0.3 V CFG1, CFG2 to Ground −0.3 V to +6.5 V
Table 4. Thermal Resistance
EN1/ENALL, EN2/DL12, EN3/UV, −0.3 V to +6.5 V
Package Type θJA θJC Unit
EN4/DL34 to Ground CP-40-10 40 11.1 °C/W GPIO to Ground −0.3 V to +6.5 V RT to Ground −0.3 V to +6.5 V VREF to Ground −0.3 V to +6.5 V
ESD CAUTION
FB1, FB2, FB3, FB4 to Ground 1 −0.3 V to +6.5 V COMP1, COMP2, COMP3, COMP4 −0.3 V to +6.5 V to Ground VSET1, VSET2, VSET3, VSET4 to −0.3 V to +6.5 V Ground Storage Temperate Range −65°C to +150°C Operational Junction Temperature −40°C to +125°C Range 1 The rating for the FB1, FB2, FB3, and FB4 pins applies to the adjustable output voltage models of the ADP5014. Rev. A | Page 7 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK LOW NOISE OUTPUT DESIGN PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
Stresses at or above those listed under Absolute Maximum
Parameter Rating
Ratings may cause permanent damage to the product. This is a AVIN to Ground −0.3 V to +6.5 V stress rating only; functional operation of the product at these PVIN1 to PGND1 −0.3 V to +6.5 V or any other conditions above those indicated in the operational PVIN2 to PGND2 −0.3 V to +6.5 V section of this specification is not implied. Operation beyond PVIN3 to PGND3 −0.3 V to +6.5 V the maximum operating conditions for extended periods may PVIN4 to PGND4 −0.3 V to +6.5 V affect product reliability. SW1 to PGND1 −0.3 V to +6.5 V
THERMAL RESISTANCE
SW2 to PGND2 −0.3 V to +6.5 V Thermal performance is directly linked to printed circuit board SW3 to PGND3 −0.3 V to +6.5 V (PCB) design and operating environment. Close attention to SW4 to PGND4 −0.3 V to +6.5 V PCB thermal design is required. PGND to Ground −0.3 V to + 0.3 V CFG1, CFG2 to Ground −0.3 V to +6.5 V
Table 4. Thermal Resistance
EN1/ENALL, EN2/DL12, EN3/UV, −0.3 V to +6.5 V
Package Type θJA θJC Unit
EN4/DL34 to Ground CP-40-10 40 11.1 °C/W GPIO to Ground −0.3 V to +6.5 V RT to Ground −0.3 V to +6.5 V VREF to Ground −0.3 V to +6.5 V
ESD CAUTION
FB1, FB2, FB3, FB4 to Ground 1 −0.3 V to +6.5 V COMP1, COMP2, COMP3, COMP4 −0.3 V to +6.5 V to Ground VSET1, VSET2, VSET3, VSET4 to −0.3 V to +6.5 V Ground Storage Temperate Range −65°C to +150°C Operational Junction Temperature −40°C to +125°C Range 1 The rating for the FB1, FB2, FB3, and FB4 pins applies to the adjustable output voltage models of the ADP5014. Rev. A | Page 7 of 34 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUIT GENERAL DESCRIPTION REVISION HISTORY DETAILED FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS BUCK REGULATOR SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BUCK REGULATOR OPERATIONAL MODES PWM Mode PSM Mode FPWM and Automatic PWM/PSM Modes LOW NOISE ARCHITECTURE INTERNAL REFERENCE (VREF) ADJUSTABLE OUTPUT VOLTAGE FUNCTION CONFIGURATIONS (CFG1 AND CFG2) PARALLEL OPERATION MANUAL/SEQUENCE MODE Manual Mode (Precision Enable) Sequence Mode GENERAL PURPOSE INPUT/OUTPUT (GPIO) OSCILLATOR Phase Shift SYNCHRONIZATION INPUT/OUTPUT POWER-GOOD FUNCTION UV COMPARATOR (SEQUENCE MODE ONLY) SOFT START STARTUP WITH PRECHARGED OUTPUT CURRENT-LIMIT PROTECTION FREQUENCY FOLD BACK SHORT-CIRCUIT PROTECTION (SCP) OVERVOLTAGE PROTECTION UNDERVOLTAGE LOCKOUT ACTIVE OUTPUT DISCHARGE SWITCH THERMAL SHUTDOWN APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL PROGRAMMING THE OUTPUT VOLTAGE VOLTAGE CONVERSION LIMITATIONS CURRENT-LIMIT SETTING SOFT START SETTING INDUCTOR SELECTION OUTPUT CAPACITOR SELECTION INPUT CAPACITOR SELECTION PROGRAMMING THE UVLO INPUT COMPENSATION COMPONENTS DESIGN POWER DISSIPATION Buck Regulator Power Dissipation Power Switch Conduction Loss (PCOND) Switching Loss (PSW) Transition Loss (PTRAN) Thermal Shutdown JUNCTION TEMPERATURE DESIGN EXAMPLES SETTING THE SWITCHING FREQUENCY SETTING THE OUTPUT VOLTAGE SETTING THE CONFIGUATIONS (CFG1 AND CFG2) SELECTING THE INDUCTOR SELECTING THE OUTPUT CAPACITOR DESIGNING THE COMPENSATION NETWORK LOW NOISE OUTPUT DESIGN PCB LAYOUT RECOMMENDATIONS TYPICAL APPLICATION CIRCUITS FACTORY PROGRAMMABLE OPTIONS FACTORY DEFAULT OPTIONS OUTLINE DIMENSIONS ORDERING GUIDE
