Datasheet SLG46811 (Dialog Semiconductor) - 4
| Manufacturer | Dialog Semiconductor |
| Description | GreenPAK Programmable Mixed-signal Matrix |
| Pages / Page | 168 / 4 — SLG46811. GreenPAK Programmable Mixed-Signal Matrix. Preliminary. … |
| File Format / Size | PDF / 2.3 Mb |
| Document Language | English |
SLG46811. GreenPAK Programmable Mixed-Signal Matrix. Preliminary. Figures. Datasheet. Revision 2.2. 3-Feb-2021
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SLG46811 GreenPAK Programmable Mixed-Signal Matrix Preliminary Figures
Figure 1: Block Diagram... 7 Figure 2: Steps to Create a Custom GreenPAK Device...22 Figure 3: GPI Structure Diagram..23 Figure 4: GPIO with I2C Mode IO Structure Diagram...24 Figure 5: Matrix OE IO Structure Diagram ...25 Figure 6: Register OE IO Structure Diagram..26 Figure 7: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C ...27 Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range ..27 Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C ...28 Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range ..28 Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C ...29 Figure 12: Connection Matrix ...30 Figure 13: Connection Matrix Usage Example...30 Figure 14: 2-bit LUT0 or DFF0 ...37 Figure 15: 2-bit LUT1 or DFF1 ...38 Figure 16: 2-bit LUT2 or PGen ...39 Figure 17: PGen Timing Diagram...40 Figure 18: 3-bit LUT4 or DFF6 or Shift Register 0 ...41 Figure 19: 3-bit LUT5 or DFF7 or Shift Register 1 ...42 Figure 20: 3-bit LUT6 or DFF8 or Shift Register 2 ...42 Figure 21: 3-bit LUT7 or DFF9 or Shift Register 3 ...43 Figure 22: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation ...43 Figure 23: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1 ...44 Figure 24: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 1 ..44 Figure 25: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 2 ..45 Figure 26: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0 ...45 Figure 27: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 1 ..46 Figure 28: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 2 ..46 Figure 29: 3-bit LUT0 or DFF2 ...48 Figure 30: 3-bit LUT1 or DFF3 ...49 Figure 31: 3-bit LUT2 or DFF4 ...49 Figure 32: 3-bit LUT3 or DFF5 ...50 Figure 33: 4-bit LUT0 or DFF16 ...51 Figure 34: Possible Connections Inside Multi-Function Macrocell ...53 Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF10, CNT/DLY0/FSM)...54 Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF11, CNT/DLY1) ...55 Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF12, CNT/DLY2) ...56 Figure 38: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF13, CNT/DLY3) ...57 Figure 39: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF14, CNT/DLY4) ...58 Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF15, CNT/DLY5) ...59 Figure 41: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ..62 Figure 42: Delay Mode Timing Diagram for Different Edge Select Modes...63 Figure 43: Counter Mode Timing Diagram without Two DFFs Synced Up ..63 Figure 44: Counter Mode Timing Diagram with Two DFFs Synced Up ...64 Figure 45: One-Shot Function Timing Diagram..65 Figure 46: Frequency Detection Mode Timing Diagram...66 Figure 47: Edge Detection Mode Timing Diagram ...67 Figure 48: Delayed Edge Detection Mode Timing Diagram ...68 Figure 49: Counter Value, Counter Data = 3..69 Figure 50: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for CNT Data = 3 ..69 Figure 51: Multichannel Sampling ACMP Block Diagram ..71 Figure 52: Timing Diagrams for MS ACMP. Edge Sensitive Mode. OSC0 and BG are Forced On...72 Figure 53: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 and BG are Forced On...72 Figure 54: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 is in Auto Power On Mode. BG is Forced On ..73 Figure 55: Typical Propagation Delay vs. Vref for MS ACMP at T = 25 °C, Gain = 1, Hysteresis = 0, Regular Mode ..74
Datasheet Revision 2.2 3-Feb-2021
CFR0011-120-00 4 of 168 © 2021 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 12 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 I2C Pins Electrical Characteristics 3.6 Macrocells Current Consumption 3.7 Timing Characteristics 3.8 Counter/Delay Characteristics 3.9 Oscillator Characteristics 3.9.1 OSC Power-On Delay 3.10 MS ACMP Characteristics 3.11 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-up/down during Power-up 5.5 GPI Structure 5.5.1 GPI Structure (for GPI) 5.6 GPIO with I2C Mode IO Structure 5.6.1 GPIO with I2C Mode Structure (for GPIO0 and GPIO1) 5.7 Matrix OE IO Structure 5.7.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO7, GPIO8) 5.8 Register OE IO Structure 5.8.1 Register OE IO Structure (for GPIO4, GPIO5, GPIO6) 5.9 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.2 2-bit LUT or Programmable Pattern Generator 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells Or Shift Register Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.4 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.5 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.5.1 4-Bit LUT Macrocell Used as 4-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY5 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY5 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY5 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY5 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY5 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY5 8.2.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 FSM Timing Diagrams 9 Multichannel Sampling Analog Comparator 9.1 Multichannel Sampling ACMP Block Diagram 9.2 MS ACMP Timing Diagrams 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 13 Clocking 13.1 OSC General description 13.2 Oscillator0 (2.048 kHz/10 kHz) 13.3 Oscillator1 (25 MHz) 13.4 CNT/DLY Clock Scheme 13.5 External Clocking 13.5.1 GPI Source for Oscillator0 (2.048kHz/10 kHz) 13.5.2 GPIO Source for Oscillator1 (25 MHz) 13.6 Oscillators Power-On Delay 13.7 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 I2C Serial Command Register Map 15.6 I2C Additional Options 15.6.1 I2C Byte Write Bit Masking 16 Extended Pattern Generator 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking Definitions 19.1 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, before February 1, 2021 19.2 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, after February 1, 2021 20 Package Information 20.1 Package outlines FOR STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package 20.2 Moisture Sensitivity Level 20.3 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 22 Layout Guidelines 22.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package Glossary Revision History
SLG46811 GreenPAK Programmable Mixed-Signal Matrix Preliminary Figures
Figure 1: Block Diagram... 7 Figure 2: Steps to Create a Custom GreenPAK Device...22 Figure 3: GPI Structure Diagram..23 Figure 4: GPIO with I2C Mode IO Structure Diagram...24 Figure 5: Matrix OE IO Structure Diagram ...25 Figure 6: Register OE IO Structure Diagram..26 Figure 7: Typical High Level Output Current vs. High Level Output Voltage at T = 25 °C ...27 Figure 8: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C, Full Range ..27 Figure 9: Typical Low Level Output Current vs. Low Level Output Voltage, 1x Drive at T = 25 °C ...28 Figure 10: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C, Full Range ..28 Figure 11: Typical Low Level Output Current vs. Low Level Output Voltage, 2x Drive at T = 25 °C ...29 Figure 12: Connection Matrix ...30 Figure 13: Connection Matrix Usage Example...30 Figure 14: 2-bit LUT0 or DFF0 ...37 Figure 15: 2-bit LUT1 or DFF1 ...38 Figure 16: 2-bit LUT2 or PGen ...39 Figure 17: PGen Timing Diagram...40 Figure 18: 3-bit LUT4 or DFF6 or Shift Register 0 ...41 Figure 19: 3-bit LUT5 or DFF7 or Shift Register 1 ...42 Figure 20: 3-bit LUT6 or DFF8 or Shift Register 2 ...42 Figure 21: 3-bit LUT7 or DFF9 or Shift Register 3 ...43 Figure 22: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation ...43 Figure 23: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1 ...44 Figure 24: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 1 ..44 Figure 25: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nReset Option, DFF Initial Value: 1, Case 2 ..45 Figure 26: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0 ...45 Figure 27: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 1 ..46 Figure 28: DFF6 to DFF9 or Shift Register 0 to Shift Register 3 Operation, nSet Option, DFF Initial Value: 0, Case 2 ..46 Figure 29: 3-bit LUT0 or DFF2 ...48 Figure 30: 3-bit LUT1 or DFF3 ...49 Figure 31: 3-bit LUT2 or DFF4 ...49 Figure 32: 3-bit LUT3 or DFF5 ...50 Figure 33: 4-bit LUT0 or DFF16 ...51 Figure 34: Possible Connections Inside Multi-Function Macrocell ...53 Figure 35: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT8/DFF10, CNT/DLY0/FSM)...54 Figure 36: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT9/DFF11, CNT/DLY1) ...55 Figure 37: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT10/DFF12, CNT/DLY2) ...56 Figure 38: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT11/DFF13, CNT/DLY3) ...57 Figure 39: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT12/DFF14, CNT/DLY4) ...58 Figure 40: 8-bit Multi-Function Macrocells Block Diagram (3-bit LUT13/DFF15, CNT/DLY5) ...59 Figure 41: Delay Mode Timing Diagram, Edge Select: Both, Counter Data: 3 ..62 Figure 42: Delay Mode Timing Diagram for Different Edge Select Modes...63 Figure 43: Counter Mode Timing Diagram without Two DFFs Synced Up ..63 Figure 44: Counter Mode Timing Diagram with Two DFFs Synced Up ...64 Figure 45: One-Shot Function Timing Diagram..65 Figure 46: Frequency Detection Mode Timing Diagram...66 Figure 47: Edge Detection Mode Timing Diagram ...67 Figure 48: Delayed Edge Detection Mode Timing Diagram ...68 Figure 49: Counter Value, Counter Data = 3..69 Figure 50: CNT/FSM Mode Timing Diagram (Set Rising Edge Mode, Oscillator Is Forced On, UP = 1) for CNT Data = 3 ..69 Figure 51: Multichannel Sampling ACMP Block Diagram ..71 Figure 52: Timing Diagrams for MS ACMP. Edge Sensitive Mode. OSC0 and BG are Forced On...72 Figure 53: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 and BG are Forced On...72 Figure 54: Timing Diagrams for MS ACMP. Level Sensitive Mode. OSC0 is in Auto Power On Mode. BG is Forced On ..73 Figure 55: Typical Propagation Delay vs. Vref for MS ACMP at T = 25 °C, Gain = 1, Hysteresis = 0, Regular Mode ..74
Datasheet Revision 2.2 3-Feb-2021
CFR0011-120-00 4 of 168 © 2021 Dialog Semiconductor Document Outline General Description Key Features Applications 1 Block Diagram 2 Pinout 2.1 Pin Configuration - STQFN- 12 3 Characteristics 3.1 Absolute Maximum Ratings 3.2 Electrostatic Discharge Ratings 3.3 Recommended Operating Conditions 3.4 Electrical Characteristics 3.5 I2C Pins Electrical Characteristics 3.6 Macrocells Current Consumption 3.7 Timing Characteristics 3.8 Counter/Delay Characteristics 3.9 Oscillator Characteristics 3.9.1 OSC Power-On Delay 3.10 MS ACMP Characteristics 3.11 Analog Temperature Sensor Characteristics 4 User Programmability 5 IO Pins 5.1 GPIO Pins 5.2 GPI Pins 5.3 Pull-Up/Down Resistors 5.4 Fast Pull-up/down during Power-up 5.5 GPI Structure 5.5.1 GPI Structure (for GPI) 5.6 GPIO with I2C Mode IO Structure 5.6.1 GPIO with I2C Mode Structure (for GPIO0 and GPIO1) 5.7 Matrix OE IO Structure 5.7.1 Matrix OE IO Structure (for GPIO2, GPIO3, GPIO7, GPIO8) 5.8 Register OE IO Structure 5.8.1 Register OE IO Structure (for GPIO4, GPIO5, GPIO6) 5.9 IO Typical Performance 6 Connection Matrix 6.1 Matrix Input Table 6.2 Matrix Output Table 6.3 Connection Matrix Virtual Inputs 6.4 Connection Matrix Virtual Outputs 7 Combination Function Macrocells 7.1 2-Bit LUT or D Flip-Flop Macrocells 7.1.1 2-Bit LUT or D Flip-Flop Macrocell Used as 2-Bit LUT 7.2 2-bit LUT or Programmable Pattern Generator 7.3 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells Or Shift Register Macrocells 7.3.1 3-Bit LUT or D Flip-Flop Macrocells Used as 3-Bit LUTs 7.4 3-Bit LUT or D Flip-Flop with Set/Reset Macrocells 7.5 4-Bit LUT or D Flip-Flop with Set/Reset Macrocell 7.5.1 4-Bit LUT Macrocell Used as 4-Bit LUT 8 Multi-Function Macrocells 8.1 3-Bit LUT or DFF/Latch with 8-Bit Counter/Delay Macrocells 8.1.1 3-Bit LUT or 8-Bit CNT/DLY Block Diagrams 8.1.2 3-Bit LUT or CNT/DLYs Used as 3-Bit LUTs 8.2 CNT/DLY Timing Diagrams 8.2.1 Delay Mode CNT/DLY0 to CNT/DLY5 8.2.2 Count Mode (Count Data: 3), Counter Reset (Rising Edge Detect) CNT/DLY0 to CNT/DLY5 8.2.3 One-Shot Mode CNT/DLY0 to CNT/DLY5 8.2.4 Frequency Detection Mode CNT/DLY0 to CNT/DLY5 8.2.5 Edge Detection Mode CNT/DLY1 to CNT/DLY5 8.2.6 Delayed Edge Detection Mode CNT/DLY0 to CNT/DLY5 8.2.7 Difference in Counter Value for Counter, Delay, One-Shot, and Frequency Detect Modes 8.3 FSM Timing Diagrams 9 Multichannel Sampling Analog Comparator 9.1 Multichannel Sampling ACMP Block Diagram 9.2 MS ACMP Timing Diagrams 9.3 ACMP Typical Performance 10 Programmable Delay/Edge Detector 10.1 Programmable Delay Timing Diagram - Edge Detector OUTPUT 11 Additional Logic Function. Deglitch Filter 12 Voltage Reference 12.1 Voltage Reference Overview 12.2 Vref Selection Table 13 Clocking 13.1 OSC General description 13.2 Oscillator0 (2.048 kHz/10 kHz) 13.3 Oscillator1 (25 MHz) 13.4 CNT/DLY Clock Scheme 13.5 External Clocking 13.5.1 GPI Source for Oscillator0 (2.048kHz/10 kHz) 13.5.2 GPIO Source for Oscillator1 (25 MHz) 13.6 Oscillators Power-On Delay 13.7 Oscillators Accuracy 14 Power-On Reset 14.1 General Operation 14.2 POR Sequence 14.3 Macrocells Output States During POR Sequence 14.3.1 Initialization 14.3.2 Power-Down 15 I2C Serial Communications Macrocell 15.1 I2C Serial Communications Macrocell Overview 15.2 I2C Serial Communications Device Addressing 15.3 I2C Serial General Timing 15.4 I2C Serial Communications Commands 15.4.1 Byte Write Command 15.4.2 Sequential Write Command 15.4.3 Current Address Read Command 15.4.4 Random Read Command 15.4.5 Sequential Read Command 15.4.6 I2C Serial Reset Command 15.5 I2C Serial Command Register Map 15.6 I2C Additional Options 15.6.1 I2C Byte Write Bit Masking 16 Extended Pattern Generator 17 Analog Temperature Sensor 18 Register Definitions 18.1 Register Map 19 Package Top Marking Definitions 19.1 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, before February 1, 2021 19.2 STQFN 12L 1.6 mm x 1.6 mm 0.4P FC, after February 1, 2021 20 Package Information 20.1 Package outlines FOR STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package 20.2 Moisture Sensitivity Level 20.3 Soldering Information 21 Ordering Information 21.1 Tape and Reel Specifications 21.2 Carrier Tape Drawing and Dimensions 22 Layout Guidelines 22.1 STQFN 12L 1.6 mm x 1.6 mm x 0.55 mm 0.4P FC Package Glossary Revision History
