Datasheet STK14C88C (Infineon) - 3
| Manufacturer | Infineon |
| Description | 256-Kbit (32K x 8) nvSRAM |
| Pages / Page | 21 / 3 — STK14C88C. Pinout. Figure 1. 32-pin CDIP pinout. (TOP). Pin Definitions. … |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
STK14C88C. Pinout. Figure 1. 32-pin CDIP pinout. (TOP). Pin Definitions. Pin Name. Alternate. I/O Type. Description
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STK14C88C Pinout Figure 1. 32-pin CDIP pinout
VCAP 1 32 VCC A14 2 31 HSB A12 3 30 W A7 4 29 A13 A 5 28 A 6 8 A5 6 27 A9 A4 7 26 A11 A3 8 25 G
(TOP)
NC 9 24 NC A2 10 23 A10 A1 11 22 E A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3
Pin Definitions Pin Name Alternate Pin Name I/O Type Description
A0–A14 Input Address inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ0–DQ7 Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation. W WE Input Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. E CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. G OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tri-stated on deasserting OE HIGH. VSS Ground Ground for the device. Must be connected to the ground of the system. VCC Power supply Power supply inputs to the device. HSB Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress. When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection is optional). VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No connect No connect. This pin is not connected to the die. Document Number: 002-23965 Rev. *A Page 3 of 21 Document Outline 256-Kbit (32K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
VCAP 1 32 VCC A14 2 31 HSB A12 3 30 W A7 4 29 A13 A 5 28 A 6 8 A5 6 27 A9 A4 7 26 A11 A3 8 25 G
(TOP)
NC 9 24 NC A2 10 23 A10 A1 11 22 E A0 12 21 DQ7 DQ0 13 20 DQ6 DQ1 14 19 DQ5 DQ2 15 18 DQ4 VSS 16 17 DQ3
Pin Definitions Pin Name Alternate Pin Name I/O Type Description
A0–A14 Input Address inputs. Used to select one of the 32,768 bytes of the nvSRAM. DQ0–DQ7 Input/Output Bidirectional data I/O Lines. Used as input or output lines depending on operation. W WE Input Write Enable input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is written to the specific address location. E CE Input Chip Enable input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip. G OE Input Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read cycles. I/O pins are tri-stated on deasserting OE HIGH. VSS Ground Ground for the device. Must be connected to the ground of the system. VCC Power supply Power supply inputs to the device. HSB Input/Output Hardware STORE Busy (HSB). When LOW, this output indicates that a Hardware STORE is in progress. When pulled LOW, external to the chip, it initiates a nonvolatile STORE operation. After each Hardware and Software STORE operation HSB is driven HIGH for a short time (tHHHD) with standard output high current and then a weak internal pull-up resistor keeps this pin HIGH (external pull-up resistor connection is optional). VCAP Power supply AutoStore capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to nonvolatile elements. NC No connect No connect. This pin is not connected to the die. Document Number: 002-23965 Rev. *A Page 3 of 21 Document Outline 256-Kbit (32K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
