Datasheet STK14C88C (Infineon) - 10
| Manufacturer | Infineon |
| Description | 256-Kbit (32K x 8) nvSRAM |
| Pages / Page | 21 / 10 — STK14C88C. AC Switching Characteristics. Parameters. 35 ns. Description. … |
| File Format / Size | PDF / 458 Kb |
| Document Language | English |
STK14C88C. AC Switching Characteristics. Parameters. 35 ns. Description. Unit. Cypress. Parameter. Alt Parameter. Min. Max. SRAM Read Cycle
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STK14C88C AC Switching Characteristics
Over the Operating Range
Parameters
[9]
35 ns Description Unit Cypress Parameter Alt Parameter Min Max SRAM Read Cycle
tACE tACS Chip enable access time – 35 ns t [10] t RC RC Read cycle time 35 – ns t [11] t AA AA Address access time – 35 ns t t DOE OE Output enable to data valid – 15 ns t [11] t OHA OH Output hold after address change 3 – ns t [12, 13] t LZCE LZ Chip enable to output active 3 – ns t [12, 13] t HZCE HZ Chip disable to output inactive – 13 ns t [12, 13] t LZOE OLZ Output enable to output active 0 – ns t [12, 13] t HZOE OHZ Output disable to output inactive – 13 ns t [12] t PU PA Chip enable to power active 0 – ns t [12] t PD PS Chip disable to power standby – 35 ns
SRAM Write Cycle
tWC tWC Write cycle time 35 – ns tPWE tWP Write pulse width 25 – ns tSCE tCW Chip enable to end of write 25 – ns tSD tDW Data setup to end of write 12 – ns tHD tDH Data hold after end of write 0 – ns tAW tAW Address setup to end of write 25 – ns tSA tAS Address setup to start of write 0 – ns tHA tWR Address hold after end of write 0 – ns t [12, 13, 14] t HZWE WZ Write enable to output disable – 13 ns t [12, 13] t LZWE OW Output active after end of write 3 – ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC (typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 3 on page 9. 10. WE must be HIGH during SRAM read cycles. 11. Device is continuously selected with CE and OE LOW. 12. These parameters are guaranteed by design and are not tested. 13. Measured ±200 mV from steady state output voltage. 14. If WE is low when CE goes low, the outputs remain in the high impedance state. Document Number: 002-23965 Rev. *A Page 10 of 21 Document Outline 256-Kbit (32K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
STK14C88C AC Switching Characteristics
Over the Operating Range
Parameters
[9]
35 ns Description Unit Cypress Parameter Alt Parameter Min Max SRAM Read Cycle
tACE tACS Chip enable access time – 35 ns t [10] t RC RC Read cycle time 35 – ns t [11] t AA AA Address access time – 35 ns t t DOE OE Output enable to data valid – 15 ns t [11] t OHA OH Output hold after address change 3 – ns t [12, 13] t LZCE LZ Chip enable to output active 3 – ns t [12, 13] t HZCE HZ Chip disable to output inactive – 13 ns t [12, 13] t LZOE OLZ Output enable to output active 0 – ns t [12, 13] t HZOE OHZ Output disable to output inactive – 13 ns t [12] t PU PA Chip enable to power active 0 – ns t [12] t PD PS Chip disable to power standby – 35 ns
SRAM Write Cycle
tWC tWC Write cycle time 35 – ns tPWE tWP Write pulse width 25 – ns tSCE tCW Chip enable to end of write 25 – ns tSD tDW Data setup to end of write 12 – ns tHD tDH Data hold after end of write 0 – ns tAW tAW Address setup to end of write 25 – ns tSA tAS Address setup to start of write 0 – ns tHA tWR Address hold after end of write 0 – ns t [12, 13, 14] t HZWE WZ Write enable to output disable – 13 ns t [12, 13] t LZWE OW Output active after end of write 3 – ns
Notes
9. Test conditions assume signal transition time of 3 ns or less, timing reference levels of VCC/2, input pulse levels of 0 to VCC (typ), and output loading of the specified IOL/IOH and load capacitance shown in Figure 3 on page 9. 10. WE must be HIGH during SRAM read cycles. 11. Device is continuously selected with CE and OE LOW. 12. These parameters are guaranteed by design and are not tested. 13. Measured ±200 mV from steady state output voltage. 14. If WE is low when CE goes low, the outputs remain in the high impedance state. Document Number: 002-23965 Rev. *A Page 10 of 21 Document Outline 256-Kbit (32K × 8) nvSRAM Features Functional Description Logic Block Diagram Contents Pinout Pin Definitions Device Operation SRAM Read SRAM Write AutoStore Operation Hardware STORE Operation Hardware RECALL (Power-up) Software STORE Software RECALL Preventing AutoStore Data Protection Maximum Ratings Operating Range DC Electrical Characteristics Data Retention and Endurance Capacitance Thermal Resistance AC Test Loads AC Test Conditions AC Switching Characteristics SRAM Read Cycle SRAM Write Cycle Switching Waveforms AutoStore/Power-up RECALL Switching Waveforms Software Controlled STORE/RECALL Cycle Switching Waveforms Hardware STORE Cycle Switching Waveforms Truth Table For SRAM Operations Ordering Information Ordering Code Definitions for Industrial Temperature Ordering Code Definitions for Military Temperature Package Diagram Acronyms Document Conventions Units of Measure Document History Page Sales, Solutions, and Legal Information Worldwide Sales and Design Support Products PSoC® Solutions Cypress Developer Community Technical Support
