Datasheet 6EDL7141 (Infineon) - 2

6EDL7141
Datasheet
Potential Applications
Power tools Gardening tools 3 Phase BLDC and PMSM motors E-bikes Robotics, RC toys, consumer drones and multi-copters Pumps and fans
Product Description
6EDL7141 is a gate driver IC for 3 phase BLDC or PMSM motor drive applications. It provides three half- bridge drivers, each capable of driving a high side and low side N-type MOSFET. The gate driver is also provided with programmable dead time delays for preventing current shoot- through between HS and LS switches in normal operation. Separate charge pumps for low and high side gate drivers support 100% duty cycle and low voltage supply operation. Supplies for the gate drivers are programmable to one of the following levels: 7 V, 10 V, 12 V or 15 V. Additionally, the slew rate of the driving signal can be programmed with fine granularity to reduce EMI emissions. An integrated synchronous buck converter provides an efficient supply of current to the rest of the system. However, power tool systems require high precision current measurements, involving a very precise ADC reference voltage. For that purpose, 6EDL7141 uses a linear voltage regulator (up to 300mA), powered by the buck converter to supply the MCU and other sensitive components in the system. With this advanced power supply architecture, not only the best possible signal quality is achieved, but also the power efficiency is optimized at any input and output condition. 6EDL7141 includes three current sense amplifiers for accurate current measurements that support bi- directional low side current sensing with programmable gain. RDSON sensing is supported through internal connection of the phase nodes to the current sense amplifiers inputs. Temperature compensation if needed shall be provided by the user application. Outputs of current sense amplifiers support both 3.3V and 5V allowing most commercial controllers to be compatible. Low noise, low settling times and high accuracy are the main features of the integrated operational amplifiers. An internal buffer can be used to offset the sense amplifier outputs for optimizing the dynamic range. The device provides numerous protection features for improving application robustness during adverse conditions like monitoring of power supply voltages as well as system parameters. The failure behavior, threshold voltages and filter times of the supervisions of the device are adjustable via SPI. Monitored aspects include inverter currents, gate drive voltages and currents, device temperature, and rotor locked. When a fault occurs, the device stops driving and pulls nFAULT pin low, in order to prevent system damage or other possible malfunction. This signal can be connected to a microcontroller to inform the processor that a fault has happened. The microcontroller can request more information on the fault via SPI commands. The integrated SPI interface can be used to configure 6EDL7141for the application. The SPI provides both detailed fault reporting and flexible parameter settings such as gain of the current sense amplifiers, slew rate control of the gate drivers, various protection features or gate driver voltage.
Datasheet
2
<Revision 1.00> <2021- 06-02>
Document Outline Product Feature Summary Potential Applications Product Description System Block Diagram Package Description 1 Pin Configuration 1.1 Pin Assignment 1.2 Pin Definitions and Functions 2 General Product Characteristics 2.1 Absolute Maximum Ratings 2.2 Recommended Operating Conditions 2.3 ESD Robustness 2.4 Thermal Resistance 2.5 Electrical Characteristics 2.6 Electrical Characteristic Graphs 3 Product Features 3.1 Functional Block Diagram 3.2 PWM Modes 3.2.1 PWM with 6 Independent Inputs – 6PWM 3.2.2 PWM with 3 Independent Inputs – 3PWM 3.2.3 PWM with 1 Input and Commutation Pattern – 1PWM 3.2.4 PWM with 1 Input and Commutation with Hall Sensor Inputs – 1PWM with Hall Sensors 3.2.5 PWM with 1 Input and Commutation with Hall Sensor Inputs and Alternating Recirculation – 1PWM with Hall Sensors and Alternating Recirculation 3.2.6 PWM Braking Modes 3.2.7 Dead Time Insertion 3.3 Integrated Three Phase Gate Driver 3.3.1 Gate Driver Architecture 3.3.2 Slew Rate Control 3.3.2.1 Slew Rate Control Parameters and Usage 3.3.3 Gate Driver Voltage Programmability 3.4 Charge Pump Configuration 3.4.1 Charge Pump Clock Frequency Selection 3.4.2 Charge Pump Clock Spread Spectrum Feature 3.4.3 Charge Pump Pre-Charge for VCCLS 3.4.4 Charge Pump Tuning 3.4.5 Gate Driver and Charge Pumps Protections 3.4.5.1 VCCLS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.2 VCCHS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.3 Floating Gate Strong Pull Down 3.5 Power Supply System 3.5.1 Synchronous Buck Converter Description 3.5.1.1 Buck Converter Output Voltage Dependency on PVCC_SETPT 3.5.1.2 Synchronous Buck Converter Protections 3.5.2 DVDD Linear Regulator 3.5.2.1 DVDD Linear Regulator OCP 3.6 Current Sense Amplifiers 3.6.1 RDSON Sensing Mode vs Leg Shunt Mode 3.6.2 Current Shunt Amplifier Timing Mode 3.6.3 Current Shunt Amplifier Blanking Time 3.6.4 Current Sense Amplifier Offset Generation: Internal or External (VREF pin) 3.6.5 Overcurrent Comparators and DAC for Current Sense Amplifiers 3.6.5.1 OCP Use Cases 3.6.5.2 OCP Fault Reporting 3.6.5.3 OCP Fault Latching 3.6.5.4 PWM Truncation 3.6.6 Current Sense Amplifier Gain Selection 3.6.7 Current Sense Amplifier DC Calibration 3.6.8 Auto-Zero Compensation of Current Sense Amplifier 3.6.8.1 Internal Auto-Zero 3.6.8.2 External Auto-Zero Synchronization via CS_GAIN/AZ Pin 3.6.8.3 External Auto-Zero Synchronization via CS_GAIN/AZ Pin with Enhanced Sensing 3.7 Hall Comparators 3.8 Watchdog Timers 3.8.1 Buck converter watchdog 3.8.2 General Purpose Watchdog 3.8.3 Locked-Rotor Protection Watchdog Timer 3.9 Multi-Function Pins 3.9.1 EN_DRV Pin 3.9.2 VSENSE/nBRAKE Pin 3.9.3 CS_GAIN/AZ Pin 3.10 ADC Module-Analog to Digital Converter 3.10.1 ADC Measurement Sequencing and On Demand Conversion 3.10.2 Die Temperature Sensor 4 Device Start-Up 4.1 Power Supply Start-Up 4.2 Gate Driver and CSAMP Start-up 5 Device Functional States 6 Protections and Faults Handling 7 Device Programming-OTP and SPI interface 7.1.1 OTP User Programming Procedure: Loading Custom Default Values 7.1.2 SPI Communication 7.1.2.1 SPI Communication Example 8 Register Map 8.1 Device Programmability 8.2 Register Map Faults Status Register Temperature Status Register Power Supply Status Register Functional Status Register OTP Status Register ADC Status Register Charge Pumps Status Register Device ID Register Faults Clear Register Power Supply Configuration Register ADC Configuration Register PWM Configuration Register Sensor Configuration Register Watchdog Configuration Register Watchdog Configuration Register 2 Gate Driver Current Control Register Gate Driver Pre-Charge Current Control Register TDRIVE Source Control Register TDRIVE Sink Control Register Dead Time Register Charge Pump Configuration Register Current Sense Amplifier Configuration Register Current Sense Amplifier Configuration Register 2 OTP Program Register 9 Application Description 9.1 Recommended External Components 9.2 PCB Layout Recommendations 9.3 Typical Applications 10 ESD Protection 11 Package Information Revision history