Datasheet 6EDL7141 (Infineon) - 9
| Manufacturer | Infineon |
| Description | 3 phase smart gate driver |
| Pages / Page | 132 / 9 — 6EDL7141. Pin Configuration. Pin #. Pin Name. Type. Description. … |
| Revision | 01_00 |
| File Format / Size | PDF / 8.5 Mb |
| Document Language | English |
6EDL7141. Pin Configuration. Pin #. Pin Name. Type. Description. Datasheet. <Revision 1.00>. <2021-06-02>
Model Line for this Datasheet
Text Version of Document
6EDL7141
Datasheet
Pin Configuration Pin # Pin Name IO Type Description
Output of low side charge pump. Connect a capacitor from VCCLS to 23 VCCLS - P PGND. Output of high side charge pump. Connect a capacitor from VCCHS to 24 VCCHS - P PVDD or PGND High side gate driving signal for phase C. Not connected or connected 25 GHC O A to PVDD if not used High side source connection (phase node) for phase C. 26 SHC IO A Positive input of shunt amplifier C for RDSON sensing. Not connected if not used 27 N.C. - - Not connected 28 GLC O A Low side gate driving signal for phase C. Not connected if not used Low side source connection for phase C. 29 SLC IO A Positive input of shunt amplifier C for shunt sensing. Short to PGND if not used Current sense amplifier negative input for phase C. Short to PGND or 30 CSNC I A DGND if not used Current sense amplifier negative input for phase B. Short to PGND or 31 CSNB I A DGND if not used Low side source connection for phase B. 32 SLB IO A Positive input of shunt amplifier B for shunt sensing. Short to PGND if not used 33 GLB O A Low side gate driving signal for phase B. Not connected if not used 34 N.C. - - Not connected High side source connection (phase node) for phase B. 35 SHB IO A Positive input of shunt amplifier B for RDSON sensing. Not connected if not used High side gate driving signal for phase B. Not connected or connected 36 GHB O A to PVDD if not used High side gate driving signal for phase A. Not connected or connected 37 GHA O A to PVDD if not used High side source connection (phase node) for phase A. 38 SHA IO A Positive input of shunt amplifier A for RDSON sensing. Not connected if not used 39 N.C. - - Not connected 40 GLA O A Low side gate driving signal for phase A. Not connected if not used Low side source connection for phase A. 41 SLA IO A Positive input of shunt amplifier A for shunt sensing. Short to PGND if not used Current sense amplifier negative input for phase A. Short to PGND or 42 CSNA I A DGND if not used 43 CSOA O A Current sense amplifier output for phase A. Not connected if not used 44 CSOB O A Current sense amplifier output for phase B. Not connected if not used 45 CSOC O A Current sense amplifier output for phase C. Not connected if not used
Datasheet
9
<Revision 1.00> <2021-06-02>
Document Outline Product Feature Summary Potential Applications Product Description System Block Diagram Package Description 1 Pin Configuration 1.1 Pin Assignment 1.2 Pin Definitions and Functions 2 General Product Characteristics 2.1 Absolute Maximum Ratings 2.2 Recommended Operating Conditions 2.3 ESD Robustness 2.4 Thermal Resistance 2.5 Electrical Characteristics 2.6 Electrical Characteristic Graphs 3 Product Features 3.1 Functional Block Diagram 3.2 PWM Modes 3.2.1 PWM with 6 Independent Inputs – 6PWM 3.2.2 PWM with 3 Independent Inputs – 3PWM 3.2.3 PWM with 1 Input and Commutation Pattern – 1PWM 3.2.4 PWM with 1 Input and Commutation with Hall Sensor Inputs – 1PWM with Hall Sensors 3.2.5 PWM with 1 Input and Commutation with Hall Sensor Inputs and Alternating Recirculation – 1PWM with Hall Sensors and Alternating Recirculation 3.2.6 PWM Braking Modes 3.2.7 Dead Time Insertion 3.3 Integrated Three Phase Gate Driver 3.3.1 Gate Driver Architecture 3.3.2 Slew Rate Control 3.3.2.1 Slew Rate Control Parameters and Usage 3.3.3 Gate Driver Voltage Programmability 3.4 Charge Pump Configuration 3.4.1 Charge Pump Clock Frequency Selection 3.4.2 Charge Pump Clock Spread Spectrum Feature 3.4.3 Charge Pump Pre-Charge for VCCLS 3.4.4 Charge Pump Tuning 3.4.5 Gate Driver and Charge Pumps Protections 3.4.5.1 VCCLS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.2 VCCHS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.3 Floating Gate Strong Pull Down 3.5 Power Supply System 3.5.1 Synchronous Buck Converter Description 3.5.1.1 Buck Converter Output Voltage Dependency on PVCC_SETPT 3.5.1.2 Synchronous Buck Converter Protections 3.5.2 DVDD Linear Regulator 3.5.2.1 DVDD Linear Regulator OCP 3.6 Current Sense Amplifiers 3.6.1 RDSON Sensing Mode vs Leg Shunt Mode 3.6.2 Current Shunt Amplifier Timing Mode 3.6.3 Current Shunt Amplifier Blanking Time 3.6.4 Current Sense Amplifier Offset Generation: Internal or External (VREF pin) 3.6.5 Overcurrent Comparators and DAC for Current Sense Amplifiers 3.6.5.1 OCP Use Cases 3.6.5.2 OCP Fault Reporting 3.6.5.3 OCP Fault Latching 3.6.5.4 PWM Truncation 3.6.6 Current Sense Amplifier Gain Selection 3.6.7 Current Sense Amplifier DC Calibration 3.6.8 Auto-Zero Compensation of Current Sense Amplifier 3.6.8.1 Internal Auto-Zero 3.6.8.2 External Auto-Zero Synchronization via CS_GAIN/AZ Pin 3.6.8.3 External Auto-Zero Synchronization via CS_GAIN/AZ Pin with Enhanced Sensing 3.7 Hall Comparators 3.8 Watchdog Timers 3.8.1 Buck converter watchdog 3.8.2 General Purpose Watchdog 3.8.3 Locked-Rotor Protection Watchdog Timer 3.9 Multi-Function Pins 3.9.1 EN_DRV Pin 3.9.2 VSENSE/nBRAKE Pin 3.9.3 CS_GAIN/AZ Pin 3.10 ADC Module-Analog to Digital Converter 3.10.1 ADC Measurement Sequencing and On Demand Conversion 3.10.2 Die Temperature Sensor 4 Device Start-Up 4.1 Power Supply Start-Up 4.2 Gate Driver and CSAMP Start-up 5 Device Functional States 6 Protections and Faults Handling 7 Device Programming-OTP and SPI interface 7.1.1 OTP User Programming Procedure: Loading Custom Default Values 7.1.2 SPI Communication 7.1.2.1 SPI Communication Example 8 Register Map 8.1 Device Programmability 8.2 Register Map Faults Status Register Temperature Status Register Power Supply Status Register Functional Status Register OTP Status Register ADC Status Register Charge Pumps Status Register Device ID Register Faults Clear Register Power Supply Configuration Register ADC Configuration Register PWM Configuration Register Sensor Configuration Register Watchdog Configuration Register Watchdog Configuration Register 2 Gate Driver Current Control Register Gate Driver Pre-Charge Current Control Register TDRIVE Source Control Register TDRIVE Sink Control Register Dead Time Register Charge Pump Configuration Register Current Sense Amplifier Configuration Register Current Sense Amplifier Configuration Register 2 OTP Program Register 9 Application Description 9.1 Recommended External Components 9.2 PCB Layout Recommendations 9.3 Typical Applications 10 ESD Protection 11 Package Information Revision history
Datasheet
Pin Configuration Pin # Pin Name IO Type Description
Output of low side charge pump. Connect a capacitor from VCCLS to 23 VCCLS - P PGND. Output of high side charge pump. Connect a capacitor from VCCHS to 24 VCCHS - P PVDD or PGND High side gate driving signal for phase C. Not connected or connected 25 GHC O A to PVDD if not used High side source connection (phase node) for phase C. 26 SHC IO A Positive input of shunt amplifier C for RDSON sensing. Not connected if not used 27 N.C. - - Not connected 28 GLC O A Low side gate driving signal for phase C. Not connected if not used Low side source connection for phase C. 29 SLC IO A Positive input of shunt amplifier C for shunt sensing. Short to PGND if not used Current sense amplifier negative input for phase C. Short to PGND or 30 CSNC I A DGND if not used Current sense amplifier negative input for phase B. Short to PGND or 31 CSNB I A DGND if not used Low side source connection for phase B. 32 SLB IO A Positive input of shunt amplifier B for shunt sensing. Short to PGND if not used 33 GLB O A Low side gate driving signal for phase B. Not connected if not used 34 N.C. - - Not connected High side source connection (phase node) for phase B. 35 SHB IO A Positive input of shunt amplifier B for RDSON sensing. Not connected if not used High side gate driving signal for phase B. Not connected or connected 36 GHB O A to PVDD if not used High side gate driving signal for phase A. Not connected or connected 37 GHA O A to PVDD if not used High side source connection (phase node) for phase A. 38 SHA IO A Positive input of shunt amplifier A for RDSON sensing. Not connected if not used 39 N.C. - - Not connected 40 GLA O A Low side gate driving signal for phase A. Not connected if not used Low side source connection for phase A. 41 SLA IO A Positive input of shunt amplifier A for shunt sensing. Short to PGND if not used Current sense amplifier negative input for phase A. Short to PGND or 42 CSNA I A DGND if not used 43 CSOA O A Current sense amplifier output for phase A. Not connected if not used 44 CSOB O A Current sense amplifier output for phase B. Not connected if not used 45 CSOC O A Current sense amplifier output for phase C. Not connected if not used
Datasheet
9
<Revision 1.00> <2021-06-02>
Document Outline Product Feature Summary Potential Applications Product Description System Block Diagram Package Description 1 Pin Configuration 1.1 Pin Assignment 1.2 Pin Definitions and Functions 2 General Product Characteristics 2.1 Absolute Maximum Ratings 2.2 Recommended Operating Conditions 2.3 ESD Robustness 2.4 Thermal Resistance 2.5 Electrical Characteristics 2.6 Electrical Characteristic Graphs 3 Product Features 3.1 Functional Block Diagram 3.2 PWM Modes 3.2.1 PWM with 6 Independent Inputs – 6PWM 3.2.2 PWM with 3 Independent Inputs – 3PWM 3.2.3 PWM with 1 Input and Commutation Pattern – 1PWM 3.2.4 PWM with 1 Input and Commutation with Hall Sensor Inputs – 1PWM with Hall Sensors 3.2.5 PWM with 1 Input and Commutation with Hall Sensor Inputs and Alternating Recirculation – 1PWM with Hall Sensors and Alternating Recirculation 3.2.6 PWM Braking Modes 3.2.7 Dead Time Insertion 3.3 Integrated Three Phase Gate Driver 3.3.1 Gate Driver Architecture 3.3.2 Slew Rate Control 3.3.2.1 Slew Rate Control Parameters and Usage 3.3.3 Gate Driver Voltage Programmability 3.4 Charge Pump Configuration 3.4.1 Charge Pump Clock Frequency Selection 3.4.2 Charge Pump Clock Spread Spectrum Feature 3.4.3 Charge Pump Pre-Charge for VCCLS 3.4.4 Charge Pump Tuning 3.4.5 Gate Driver and Charge Pumps Protections 3.4.5.1 VCCLS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.2 VCCHS Under-Voltage Lock-Out (VCCLS UVLO) 3.4.5.3 Floating Gate Strong Pull Down 3.5 Power Supply System 3.5.1 Synchronous Buck Converter Description 3.5.1.1 Buck Converter Output Voltage Dependency on PVCC_SETPT 3.5.1.2 Synchronous Buck Converter Protections 3.5.2 DVDD Linear Regulator 3.5.2.1 DVDD Linear Regulator OCP 3.6 Current Sense Amplifiers 3.6.1 RDSON Sensing Mode vs Leg Shunt Mode 3.6.2 Current Shunt Amplifier Timing Mode 3.6.3 Current Shunt Amplifier Blanking Time 3.6.4 Current Sense Amplifier Offset Generation: Internal or External (VREF pin) 3.6.5 Overcurrent Comparators and DAC for Current Sense Amplifiers 3.6.5.1 OCP Use Cases 3.6.5.2 OCP Fault Reporting 3.6.5.3 OCP Fault Latching 3.6.5.4 PWM Truncation 3.6.6 Current Sense Amplifier Gain Selection 3.6.7 Current Sense Amplifier DC Calibration 3.6.8 Auto-Zero Compensation of Current Sense Amplifier 3.6.8.1 Internal Auto-Zero 3.6.8.2 External Auto-Zero Synchronization via CS_GAIN/AZ Pin 3.6.8.3 External Auto-Zero Synchronization via CS_GAIN/AZ Pin with Enhanced Sensing 3.7 Hall Comparators 3.8 Watchdog Timers 3.8.1 Buck converter watchdog 3.8.2 General Purpose Watchdog 3.8.3 Locked-Rotor Protection Watchdog Timer 3.9 Multi-Function Pins 3.9.1 EN_DRV Pin 3.9.2 VSENSE/nBRAKE Pin 3.9.3 CS_GAIN/AZ Pin 3.10 ADC Module-Analog to Digital Converter 3.10.1 ADC Measurement Sequencing and On Demand Conversion 3.10.2 Die Temperature Sensor 4 Device Start-Up 4.1 Power Supply Start-Up 4.2 Gate Driver and CSAMP Start-up 5 Device Functional States 6 Protections and Faults Handling 7 Device Programming-OTP and SPI interface 7.1.1 OTP User Programming Procedure: Loading Custom Default Values 7.1.2 SPI Communication 7.1.2.1 SPI Communication Example 8 Register Map 8.1 Device Programmability 8.2 Register Map Faults Status Register Temperature Status Register Power Supply Status Register Functional Status Register OTP Status Register ADC Status Register Charge Pumps Status Register Device ID Register Faults Clear Register Power Supply Configuration Register ADC Configuration Register PWM Configuration Register Sensor Configuration Register Watchdog Configuration Register Watchdog Configuration Register 2 Gate Driver Current Control Register Gate Driver Pre-Charge Current Control Register TDRIVE Source Control Register TDRIVE Sink Control Register Dead Time Register Charge Pump Configuration Register Current Sense Amplifier Configuration Register Current Sense Amplifier Configuration Register 2 OTP Program Register 9 Application Description 9.1 Recommended External Components 9.2 PCB Layout Recommendations 9.3 Typical Applications 10 ESD Protection 11 Package Information Revision history
