Datasheet ADuM1100 (Analog Devices) - 6

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ADuM1100 Data Sheet ELECTRICAL SPECIFICATIONS—3.3 V OPERATION
Al voltages are relative to their respective ground. 3.0 V ≤ VDD1 ≤ 3.6 V, 3.0 V ≤ VDD2 ≤ 3.6 V. Al minimum/maximum specifications apply over the entire recommended operation range, unless otherwise noted. All typical specifications are at TA = 25°C, VDD1 = VDD2 = 3.3 V.
Table 2. Parameter Symbol Min Typ Max Unit Test Conditions
DC SPECIFICATIONS Input Supply Current IDD1 (Q) 0.1 0.3 mA VI = 0 V or VDD1 Output Supply Current IDD2 (Q) 0.005 0.04 mA VI = 0 V or VDD1 Input Supply Current (25 Mbps) IDD1 (25) 2.0 2.8 mA 12.5 MHz logic signal frequency (See Figure 5) Output Supply Current1 (25 Mbps) IDD2 (25) 0.3 0.7 mA 12.5 MHz logic signal frequency (See Figure 6) Input Supply Current (50 Mbps) IDD1 (50) 4.0 6.0 mA 25 MHz logic signal frequency, (See Figure 5) ADuM1100BR/ADuM1100UR only Output Supply Current1 (50 Mbps) IDD2 (50) 1.2 1.6 mA 25 MHz logic signal frequency, (See Figure 6) ADuM1100BR/ADuM1100UR only Input Current II −10 +0.01 +10 µA 0 V ≤ VIN ≤ VDD1 Logic High Output Voltage VOH VDD2 − 0.1 3.3 V IO = −20 μA, VI = VIH VDD2 − 0.5 3.0 V IO = −2.5 mA, VI = VIH Logic Low Output Voltage VOL 0.0 0.1 V IO = 20 μA, VI = VIL 0.04 0.1 V IO = 400 μA, VI = VIL 0.3 0.4 V IO = 2.5 mA, VI = VIL SWITCHING SPECIFICATIONS For ADuM1100AR Minimum Pulse Width2 PW 40 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 25 Mbps CL = 15 pF, CMOS signal levels For ADuM1100BR/ADuM1100UR Minimum Pulse Width2 PW 10 20 ns CL = 15 pF, CMOS signal levels Maximum Data Rate3 50 100 Mbps CL = 15 pF, CMOS signal levels For All Grades Propagation Delay Time to Logic Low tPHL 14.5 28 ns CL = 15 pF, CMOS signal levels Output4, 5 (See Figure 8) Propagation Delay Time to Logic tPLH 15.0 28 ns CL = 15 pF, CMOS signal levels High Output4, 5 (See Figure 8) Pulse Width Distortion |tPLH − tPHL|5 PWD 0.5 3 ns CL = 15 pF, CMOS signal levels Change vs. Temperature6 10 ps/°C CL = 15 pF, CMOS signal levels Propagation Delay Skew tPSK1 15 ns CL = 15 pF, CMOS signal levels (Equal Temperature)5, 7 Propagation Delay Skew tPSK2 12 ns CL = 15 pF, CMOS signal levels (Equal Temperature, Supplies)5, 7 Output Rise/Fall Time tR, tF 3 ns CL = 15 pF, CMOS signal levels Common-Mode Transient Immunity |CML|, 25 35 kV/µs VI = 0 V or VDD1, VCM = 1000 V, at Logic Low/High Output8 |CMH| transient magnitude = 800 V Refresh Rate fr 1.1 Mbps Input Dynamic Supply Current9 IDDI (D) 0.08 mA/Mbps Output Dynamic Supply Current9 IDDO (D) 0.04 mA/Mbps Rev. K | Page 6 of 20 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ELECTRICAL SPECIFICATIONS—5 V OPERATION ELECTRICAL SPECIFICATIONS—3.3 V OPERATION ELECTRICAL SPECIFICATIONS—MIXED 5 V/3 V OR 3 V/5 V OPERATION PACKAGE CHARACTERISTICS REGULATORY INFORMATION INSULATION AND SAFETY-RELATED SPECIFICATIONS DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 INSULATION CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS APPLICATION INFORMATION PC BOARD LAYOUT PROPAGATION DELAY-RELATED PARAMETERS METHOD OF OPERATION, DC CORRECTNESS, AND MAGNETIC FIELD IMMUNITY POWER CONSUMPTION OUTLINE DIMENSIONS ORDERING GUIDE