Datasheet STGAP2HD (STMicroelectronics) - 3
| Manufacturer | STMicroelectronics |
| Description | Galvanically isolated 4 A dual gate driver |
| Pages / Page | 23 / 3 — STGAP2HD. Pin description and connection diagram. Figure 2. Pin … |
| File Format / Size | PDF / 815 Kb |
| Document Language | English |
STGAP2HD. Pin description and connection diagram. Figure 2. Pin connection (top view). Table 1. Pin description. Pin number
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STGAP2HD Pin description and connection diagram 2 Pin description and connection diagram Figure 2. Pin connection (top view)
N.C. 1 36 N.C. N.C. 2 35 GNDISO_A N.C. 3 34 GNDISO_A N.C. 4 33 CLAMP_A N.C. 5 32 GOFF_A VDD 6 31 GON_A INA 7 30 VH_A INB 8 SD 9 BRAKE 10 iLOCK 11 N.C. 12 25 CLAMP_B GND 13 24 GNDISO_B N.C. 14 23 GOFF_B 15 22 N.C. GON_B 16 N.C. 21 N.C. 17 20 N.C. VH_B N.C. 18 19 N.C.
Table 1. Pin description Pin number Pin name Type Function
6 VDD Power supply Control logic supply voltage. 7 INA Logic input Control logic input for Channel A, active high. 8 INB Logic input Control logic input for Channel B, active high. 9 SD Logic input Shutdown input, active low. 10 BRAKE Logic input Control logic input, active low. 11 iLOCK Analog input Interlocking enable/disable. 13 GND Power supply Control logic ground. 20 VH_B Power supply Channel B gate driving positive supply. 22 GON_B Analog output Channel B source output. 25 CLAMP_B Analog output Channel B Miller Clamp. 23 GOFF_B Analog output Channel B sink output. 24 GNDISO_B Power supply Channel B gate driving isolated ground. 30 VH_A Power supply Channel A gate driving positive supply. 31 GON_A Analog output Channel A source output. 33 CLAMP_A Analog output Channel A Miller Clamp. 32 GOFF_A Analog output Channel A sink output. 34, 35 GNDISO_A (1) Power supply Channel A gate driving isolated ground. 1, 2, 3, 4, 5, 12, 14, N.C. Not connected. 15, 16, 17, 18 1. Both GNDISO_A pins must be connected and shorted together.
DS13652
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Rev 1 page 3/23
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and ‘safe state’ 6.3 Control Inputs 6.4 Watchdog 6.5 Thermal shutdown protection 6.6 Standby function 6.7 Interlocking function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-36W package information 11 Suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures
STGAP2HD Pin description and connection diagram 2 Pin description and connection diagram Figure 2. Pin connection (top view)
N.C. 1 36 N.C. N.C. 2 35 GNDISO_A N.C. 3 34 GNDISO_A N.C. 4 33 CLAMP_A N.C. 5 32 GOFF_A VDD 6 31 GON_A INA 7 30 VH_A INB 8 SD 9 BRAKE 10 iLOCK 11 N.C. 12 25 CLAMP_B GND 13 24 GNDISO_B N.C. 14 23 GOFF_B 15 22 N.C. GON_B 16 N.C. 21 N.C. 17 20 N.C. VH_B N.C. 18 19 N.C.
Table 1. Pin description Pin number Pin name Type Function
6 VDD Power supply Control logic supply voltage. 7 INA Logic input Control logic input for Channel A, active high. 8 INB Logic input Control logic input for Channel B, active high. 9 SD Logic input Shutdown input, active low. 10 BRAKE Logic input Control logic input, active low. 11 iLOCK Analog input Interlocking enable/disable. 13 GND Power supply Control logic ground. 20 VH_B Power supply Channel B gate driving positive supply. 22 GON_B Analog output Channel B source output. 25 CLAMP_B Analog output Channel B Miller Clamp. 23 GOFF_B Analog output Channel B sink output. 24 GNDISO_B Power supply Channel B gate driving isolated ground. 30 VH_A Power supply Channel A gate driving positive supply. 31 GON_A Analog output Channel A source output. 33 CLAMP_A Analog output Channel A Miller Clamp. 32 GOFF_A Analog output Channel A sink output. 34, 35 GNDISO_A (1) Power supply Channel A gate driving isolated ground. 1, 2, 3, 4, 5, 12, 14, N.C. Not connected. 15, 16, 17, 18 1. Both GNDISO_A pins must be connected and shorted together.
DS13652
-
Rev 1 page 3/23
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and ‘safe state’ 6.3 Control Inputs 6.4 Watchdog 6.5 Thermal shutdown protection 6.6 Standby function 6.7 Interlocking function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-36W package information 11 Suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures
