Datasheet STGAP2HD (STMicroelectronics) - 4
| Manufacturer | STMicroelectronics |
| Description | Galvanically isolated 4 A dual gate driver |
| Pages / Page | 23 / 4 — STGAP2HD. Electrical data. 3.1. Absolute maximum ratings. Table 2. … |
| File Format / Size | PDF / 815 Kb |
| Document Language | English |
STGAP2HD. Electrical data. 3.1. Absolute maximum ratings. Table 2. Absolute maximum ratings. Symbol. Parameter. Test condition. Min. Max
Model Line for this Datasheet
Text Version of Document
STGAP2HD Electrical data 3 Electrical data 3.1 Absolute maximum ratings Table 2. Absolute maximum ratings Symbol Parameter Test condition Min. Max. Unit
VDD Logic supply voltage vs. GND -0.3 6.5 V VLOGIC Logic pins voltage vs. GND -0.3 6.5 V iLOCK Interlocking Enable vs. GND -0.3 VDD + 0.3 V Positive supply voltage VH_x -0.3 28 V (VH_x vs GNDISO_x) Voltage on gate driver outputs VOUT -0.3 VH_x + 0.3 V (GON_x , GOFF_x , CLAMP_x vs GNDISO_x) TJ Junction temperature -40 150 °C TS Storage temperature -50 150 °C ESD HBM (human body model) 2 kV
3.2 Thermal data Table 3. Thermal data Symbol Parameter Package Value Unit
Rth(JA) Thermal resistance junction to ambient SO-36W 52 °C/W
DS13652
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Rev 1 page 4/23
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and ‘safe state’ 6.3 Control Inputs 6.4 Watchdog 6.5 Thermal shutdown protection 6.6 Standby function 6.7 Interlocking function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-36W package information 11 Suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures
VDD Logic supply voltage vs. GND -0.3 6.5 V VLOGIC Logic pins voltage vs. GND -0.3 6.5 V iLOCK Interlocking Enable vs. GND -0.3 VDD + 0.3 V Positive supply voltage VH_x -0.3 28 V (VH_x vs GNDISO_x) Voltage on gate driver outputs VOUT -0.3 VH_x + 0.3 V (GON_x , GOFF_x , CLAMP_x vs GNDISO_x) TJ Junction temperature -40 150 °C TS Storage temperature -50 150 °C ESD HBM (human body model) 2 kV
3.2 Thermal data Table 3. Thermal data Symbol Parameter Package Value Unit
Rth(JA) Thermal resistance junction to ambient SO-36W 52 °C/W
DS13652
-
Rev 1 page 4/23
Document Outline Cover image Product status link / summary Features Application Description 1 Block diagram 2 Pin description and connection diagram 3 Electrical data 3.1 Absolute maximum ratings 3.2 Thermal data 3.3 Recommended operating conditions 4 Electrical characteristics 5 Isolation 6 Functional description 6.1 Gate driving power supply and UVLO 6.2 Power-up, power-down and ‘safe state’ 6.3 Control Inputs 6.4 Watchdog 6.5 Thermal shutdown protection 6.6 Standby function 6.7 Interlocking function 7 Typical application diagram 8 Layout 8.1 Layout guidelines and considerations 8.2 Layout example 9 Testing and characterization information 10 Package information 10.1 SO-36W package information 11 Suggested land pattern 12 Ordering information Revision history Contents List of tables List of figures
